Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2003-03-07
2004-07-13
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S777000
Reexamination Certificate
active
06762488
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a semiconductor device and a fabrication process thereof and, more particularly, to a semiconductor device having stacked semiconductor chips sealed in a package and a process for fabrication thereof.
DESCRIPTION OF THE RELATED ART
A standard semiconductor device has a single semiconductor chip sealed in a package. The standard semiconductor devices are mounted on a printed circuit board, and form a module. However, the standard semiconductor devices occupy wide area on the printed circuit board. This results in large electronic goods.
In order to scale down the electronic devices, the manufacturers are to make the printed circuit boards narrow and light. One of the approaches is to stack plural semiconductor chips with one another in a single semiconductor chip. The semiconductor device with stacked semiconductor chips is called as “stacked package semiconductor device”. The stacked package semiconductor devices are conducive to small electronic goods. Especially, the stacked package semiconductor devices are preferable for portable electronic goods such as, for example, handy phones and PDAs (Personal Digital Assistants).
FIG. 1
shows a typical example of the stacked package semiconductor device, which is disclosed in Japanese Patent Application laid-open No. 2001-223326. Reference numeral
1
designates the prior art stacked package semiconductor device. The prior art stacked package semiconductor device comprises a primary semiconductor flip chip
2
and a secondary flip chip
4
. The primary flip chip
2
is mounted on a printed flexible tape
3
, and the secondary flip chip
4
is mounted on a printed film
5
. A conductive pattern is printed on the printed flexible tape
3
, and the primary flip chip
2
is connected at pads thereof to the conductive pattern. Similarly, a conductive pattern is formed on the film
5
, and the pads of the secondary flip chip
4
are connected to the conductive pattern. The printed film
5
is adhered to the primary flip chip
2
so that the primary flip chip
2
is stacked with the secondary flip chip
4
.
The conductive pattern on the film
5
has electrodes
5
a
, and the conductive pattern on the tape
3
also has electrodes
3
b
. The electrodes
5
a
are connected to the electrodes
3
b
through conductive wires
6
, and solder balls
7
are connected to the conductive pattern, which includes the electrodes
3
b
, through the via holes formed in the flexible tape
3
. The primary flip chip
2
on the printed tape
3
, secondary flip chip
4
on the printed film
5
and conductive wires
6
are sealed in a piece of synthetic resin. Thus, the prior art stacked package semiconductor device
1
, which includes the primary and secondary flip chips
2
/
4
, occupies narrower than the total area to be occupied by the individual flip chips
2
and
4
.
Although the prior art stacked package semiconductor device is conducive to the reduction in occupation area, the prior art stacked package semiconductor device requires the printed films
3
/
5
for the individual flip chips
2
/
4
. The printed tape
3
and printed film
5
are so thick that the prior art stacked package semiconductor device is thick and heavy. If the prior art stacked package semiconductor devices are incorporated in desk-top type electronic goods, the thickness and weight may not be a problem. However, the weight and thickness of the prior art stacked package semiconductor device are serious in the portable electronic goods.
SUMMARY OF THE INVENTION
It is therefore an important object of the present invention to provide a stacked package semiconductor device, which is reduced in weight and thickness.
It is also an important object of the present invention to provide a process for fabricating the light thin stacked package semiconductor device.
In accordance with one aspect of the present invention, there is provided a stacked package semiconductor device comprising a semiconductor chip package including a sealing package made of a certain material and a semiconductor chip made of a semiconductor material brittler than the certain material, provided with a first group of conductive pads on a first surface thereof, sealed in the sealing package and having a second surface reverse to the first surface and exposed to the outside of the sealing package, a semiconductor element provided over the semiconductor chip and having a second group of conductive pads on a certain surface thereof, a connector electrically connected between certain conductive pads selected from the first group and corresponding conductive pads of the second group and buried in a piece of synthetic resin held in contact with the semiconductor chip package and the semiconductor element, a package in which the semiconductor chip package, the semiconductor element and the connector are sealed, and an array of external terminals electrically connected to remaining conductive pads of the first group and remaining conductive pads of the second group.
In accordance with another aspect of the present invention, there is provided a process for fabricating a stacked package semiconductor device comprising the steps of a) preparing a precursor of a semiconductor chip package including a sealing package made of a certain material and a semiconductor chip sealed in the sealing package and made of a semiconductor material brittler than the certain material, b) polishing the sealing package and the semiconductor chip for exposing a surface of the semiconductor chip to the outside of the sealing package so that the semiconductor chip package is made from the precursor, c) stacking the semiconductor chip package with a semiconductor element electrically connected to the semiconductor chip package and d) forming the semiconductor chip package and the semiconductor element into a stacked package semiconductor device.
In accordance with yet another aspect of the present invention, there is provided a semiconductor stacked package device comprising a semiconductor chip package including a sealing package formed with a hollow space, a semiconductor chip sealed in the sealing package and having conductive pads of a first group on a first surface exposed to the hollow space and a connector formed in the hollow space and having a conductive pattern exposed to the outside of the sealing package and conductive pieces selectively connected between the conductive pads of the first group and the conductive pattern, a semiconductor element stacked on the semiconductor chip package and having conductive pads of a second group selectively connected to the conductive pattern by means of other conductive pieces, an array of external terminals selectively electrically connected to the conductive pads of the first group and the conductive pads of the second group and a synthetic resin package in which the semiconductor chip package and the semiconductor element are sealed, and the array of external terminals is exposed to the outside of the synthetic resin package.
REFERENCES:
patent: 5903049 (1999-05-01), Mori
patent: 2003/0141583 (2003-07-01), Yang
Maeda Takehiko
Tsukano Jun
Cao Phat X.
NEC Electronics Corporation
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