Light print head

Incremental printing of symbolic information – Light or beam marking apparatus or processes – Scan of light

Reexamination Certificate

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Details

C347S236000, C347S224000

Reexamination Certificate

active

06710794

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a light emission array head, a method of adjusting a driving level of a driving signal for this head, and an image formation apparatus. In particular, the present invention relates to a light emission array head which is used as a recording light emission element to form a permanent visible image on a recording medium by an electrophotographic recording system, a method of adjusting a driving level of a driving signal for the light emission array head, and an image formation apparatus which contains the light emission array head.
2. Related Background Art
Conventionally, a self-scanning type LED (light emitting diode) array (called an SLED hereinafter) has been introduced in Japanese Patent Application Laid-Open Nos. 1-238962, 2-208067, 2-212170, 3-194978, 4-5872, 4-23367, 4-296579 and 5-84971, Japan Hard-copy Memoir 1991 (A-17)“Proposal of Light Emission Element Array for Light Printer in Which Driving Circuits Have Been Integrated”, IEICE (Institute of Electronics, Information and Communication Engineers) Memoir (Mar. 5, 1990)“Proposal of Self-Scanning Type Light Emission Element (SLED) Using PNPN Thristor Structure”, and the like. Thus, the SLED has been paid attention to as a recording light emission element (i.e., a light emission element used for image recording) for an image formation apparatus of an electrophotographic system.
FIG. 5
shows an example of this SLED. An operation of this SLED will be explained with reference to FIG.
5
.
As shown in
FIG. 5
, the SLED is composed of transfer thyristors (i.e., thyristors used for data transfer) ST
1
to ST
5
which are cascaded and light emission thyristors (i.e., thyristors used for light emission) SL
1
to SL
5
which are cascaded. As shown in
FIG. 5
, gate signals of the respective thyristors are set to be common. The gates of the first thyristors SL
1
and ST
1
are connected to the input part of a signal &PHgr;S, the gates of the second thyristors SL
2
and ST
2
are connected to the cathode of a diode connected to the terminal of the signal &PHgr;S, and the gates of the third thyristors SL
3
and ST
3
are connected to the cathode of a next diode.
FIGS. 6A
to
6
F are timing charts showing control signals of the SLED and on/off states of the thyristors. Further,
FIGS. 6A
to
6
F show an example that all elements are lit. Hereinafter, the data transfer and the light emission will be explained according to the timing charts shown in
FIGS. 6A
to
6
F.
The data transfer is started by changing the level of the signal &PHgr;S (
FIG. 6A
) from 0V to 5V. When the level of the signal &PHgr;S reaches 5V, a voltage Va=5V, a voltage Vb=3.7V (it is assumed that forward voltage drop of the diode is 1.3V), a voltage Vc=2.4V, a voltage Vd=1.1V, and a voltage Ve and following=0V. Further, the gate voltage of the transfer thyristor ST
1
is changed from 0V to 5V, and the gate voltage of the transfer thyristor ST
2
is changed from 0V to 3.7V, and the gate voltages of the following thyristors are changed similarly.
In this state, by changing the level of a signal &PHgr;
1
(
FIG. 6B
) from 5V to 0V, potentials of the anode, cathode and gate of the transfer thyristor ST
1
become 5V, 0V and 3.7V respectively, thereby satisfying an on condition of this thyristor. When the transfer thyristor ST
1
is turned on, this thyristor ST
1
is still in the on state even if the level of the signal &PHgr;S is changed to 0V, thereby maintaining the voltage Va≅5V. This is because the signal &PHgr;S is supplied through a resistor (not shown), and a potential between the anode and gate of the thyristor has substantially the same value when the thyristor is turned on.
Thus, even if the level of the signal &PHgr;S is changed to 0V, the on condition of the first thyristor is maintained, and a first shift operation ends. In this state, when the level of a signal &PHgr;I for the light emission thyristor (
FIG. 6D
) is changed from 5V to 0V, the condition same as the condition that the transfer thyristor is turned on is satisfied, whereby the light emission thyristor SL
1
is turned on, and a first LED is lit. When the level of the signal &PHgr;I is returned to 5V, a potential difference between the anode and cathode of the light emission thyristor becomes zero, and thus a minimum holding current of the thyristor can not be flowed, whereby the light emission thyristor SL
1
is turned off.
Next, transfer of the on condition from the transfer thyristor ST
1
to the transfer thyristor ST
2
will be explained.
Since the level of the signal &PHgr;
1
is maintained to 0V even if the light emission thyristor SL
1
is turned off, the transfer thyristor ST
1
is still on, and the gate voltage of the transfer thyristor ST
1
satisfies Va≈5V and Vb=3.7V. In this state, by changing the level of a signal &PHgr;
2
(
FIG. 6C
) from 5V to 0V, potentials of the anode, cathode and gate of the transfer thyristor ST
2
become 5V, 0V and 3.7V respectively, whereby the transfer thyristor ST
2
is turned on. After the transfer thyristor ST
2
has been turned on, when the level of the signal &PHgr;
1
is changed from 0V to 5V, the transfer thyristor is turned off similarly to turning off of the light emission thyristor SL
1
.
Thus, the on condition is shifted from the transfer thyristor ST
1
to the transfer thyristor ST
2
. Then, when the level of the signal &PHgr;I is changed from 5V to 0V, the light emission thyristor SL
1
is turned on, and the LED is lit. The reason why only the light emission thyristor corresponding to the transfer thyristor being on can emit the light is as follows. Namely, when the transfer thyristor is not on, since the gate voltages of the thyristors except for the thyristor adjacent to the thyristor being on are 0V, the on condition of the thyristor is not satisfied. With respect to the adjacent thyristor, when the light emission thyristor is turned on, the potential level of the signal &PHgr;I becomes 3.4V (corresponding to forward voltage drop of the light emission thyristor). Thus, since a potential difference between the gate and cathode of the adjacent thyristor is zero, this thyristor can not be turned on.
It was explained in the above description that the light emission thyristor is turned on by shifting the level of the signal &PHgr;I to 0V, whereby the LED is lit. In a practical image formation operation, it is of course necessary to control whether or not the LED is to be actually lit at such timing, in accordance with image data. Image data Dp shown in
FIG. 6E and a
signal &PHgr;D shown in
FIG. 6F
represent such control. Namely, the logical sum of the signal &PHgr;I and the image data Dp is obtained externally. Only when the image data Dp is 0V, a &PHgr;I terminal of the SLED actually becomes 0V, whereby the light is emitted. When the image data Dp is 5V, the &PHgr;I terminal of the SLED is maintained to 5V, whereby the light is not emitted.
Next, a packaging state of an SLED array head will be explained with reference to
FIG. 7
which illustrates appearance of the head.
SLED semiconductor chips
511
are mounted on a base substrate
512
to which a print wiring board such as a glass epoxy board, a ceramic board or the like is used. A control signal is externally supplied to a lighting control circuit (driver IC)
514
, whereby this circuit
514
generates a lighting control signal for the SLED semiconductor chips
511
. An external control signal is input from a connector
513
, power is input from a power supply circuit
532
through a power supply cable
531
, and the input signal and power are supplied to each semiconductor.
Bonding wires
515
are connected to the SLED semiconductor chips
511
, whereby the output signals &PHgr;
1
, &PHgr;
2
, &PHgr;S and &PHgr;I from the driver IC
514
and negative-electrode-side power (GND in this example) are input through these wires
515
. Numeral
516
denotes a positive-electrode-side power supply pattern (+5V in this example) which is drawn on

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