Light erasable memory and method therefor

Details Light erasable memory and method therefor Light erasable memory and method therefor

2007-01-05

2010-10-26

Smith, Bradley K (Department: 2894)

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

C438S129000, C438S130000, C438S131000, C438S132000, C365S185320, C365S185290, C257S323000, C257SE21422

Reexamination Certificate

active

07820491

ABSTRACT:
A semiconductor device has a semiconductor substrate that in turn has a top semiconductor layer portion and a major supporting portion under the top semiconductor layer portion. An interconnect layer is over the semiconductor layer. A memory array is in a portion of the top semiconductor layer portion and a portion of the interconnect layer. The memory is erased by removing at least a portion of the major supporting portion and, after the step of removing, applying light to the memory array from a side opposite the interconnect layer. The result is that the memory array receives light from the backside and is erased.

REFERENCES:
patent: 3660819 (1972-05-01), Frohman-Bentchkowsky
patent: 4213192 (1980-07-01), Christensen, Sr.
patent: 6229165 (2001-05-01), Sakai et al.
patent: 6323515 (2001-11-01), Yamazaki et al.

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