Active solid-state devices (e.g. – transistors – solid-state diode – Incoherent light emitter structure – Plural light emitting devices
Reexamination Certificate
2001-09-21
2004-04-06
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Incoherent light emitter structure
Plural light emitting devices
C257S079000, C345S082000
Reexamination Certificate
active
06717183
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a light-emitting thyristor matrix array formed on a chip, particularly to a light-emitting thyristor matrix array in which an area of the chip may be made small. The present invention further relates to a driver circuit for the array.
BACKGROUND ART
In an light-emitting element array used in a writing head of an optical printer, it is essentially required to derive the same number of lines from light-emitting elements as that of light-emitting elements. A wire bonding method is generally used for the derivation of lines. Therefore, the following problems are caused as the density of light-emitting elements is increased.
(1) A product cost becomes larger due to the increase of an area of a wire bonding pad on a light-emitting element array chip, i.e. an area of the chip.
(2) A production cost becomes larger due to the increase of the number of wire bondings.
(3) A production becomes difficult as the pitch of wire bonding becomes smaller.
(4) A product cost is increased because driver circuits, the number thereof is equal to that of light-emitting elements, are generally required.
An area of one bonding pad is several times or more compared with an area of one light-emitting element, so that the increase of light-emitting elements density leads to the increase of chip area.
In order to avoid these problems, a light-emitting diode (LED) array matrix array, a light-emitting thyristor matrix array, and so on have been proposed.
FIG. 1
shows an example of the light-emitting thyristor matrix array. According to this matrix array, a plurality of three-terminal light-emitting thyristors T
1
, T
2
, T
3
, . . . are arrayed in one line. These thyristors are divided into groups four by four. Anodes of the thyristors in each group are commonly connected to anode terminals A
1
, A
2
, A
3
, . . . , respectively, gates of the thyristors in each group are separately connected to gate-selecting lines G
1
-G
4
, and cathodes of all the thyristors are commonly connected to a cathode line K.
The lighting up of thyristors T
1
, T
2
, T
3
, . . . is determined by a combination of voltage levels of the gate-selecting lines G
1
-G
4
and voltage levels of the anode terminals A
1
, A
2
, A
3
, . . . . As this matrix array is a type of cathode common, when the cathode line K is at L level and an anode terminal A
i
is at H level while one gate-selecting line G
j
being at L level and the others H level, a light-emitting thyristor T
j+4(i−1)
is lighted up.
In a conventional light-emitting element array in which N (N is an integer≧2) light-emitting elements are arrayed, N control terminals are required to be derived in order to control N light-emitting elements. On the contrary, the number of control terminals is (N/M+M) in the light-emitting thyristor matrix array including M (M is an integer≧2) gate-selecting lines. The number of the thyristors which may be lighted up at the same time is equal to that of the anode terminals in the light-emitting thyristor matrix array. Also, the light emission duty ratio is equal to 1/M. Assuming that N is equal to 128 in the array of
FIG. 1
, the number of the anode terminals is equal to 32 since the number of the gate-selecting lines is 4.
Using the light-emitting thyristor matrix array, the number of bonding pads on a matrix array chip may be decreased. The number M of the gate-selecting lines in this structure in which the number of bonding pads may be decreased is selected in such a manner that M is an integer near to N
1/2
and N/M is an integer. For example, when M=8 or M=16 is selected in case of N=128, the number of bonding pads is 24 and this is minimum value. Therefore, it is possible to make the chip area small, resulting in the decrease of the chip cost. The circuit structure in
FIG. 1
using light-emitting thyristors has been proposed by the present applicant, and Japanese Patent has already been issued (Japanese Patent No. 2807910).
While the number of bonding pads may be decreased to the minimum value as described above, the chip area is not guaranteed to be minimum. A matrix array chip is generally sliced in parallelogram (e.g., rectangle). The length of a long side of the chip is determined by the product of the array pitch and the number of the light-emitting thyristors, and the length of a short side is principally determined by the summation of the width of one light-emitting thyristor, the width of wirings and the width bonding pads. The area required for one bonding pad is decided by the performance of a wire bonding machine, so that it is impossible for the length of a short side of the chip to be short, unless the number of rows of bonding pads is reduced. Therefore, the area of the chip is not decreased, even if the number of bonding pads is reduced.
DISCLOSURE OF THE INVENTION
The object of the present invention is to provide a light-emitting thyristor matrix array in which the area of a chip may be decreased.
In order to decrease the area of the chip, bonding pads are arrayed in one line parallel to a long side of the chip to make the length of a short side of the chip small. The bonding pads may be arrayed in one line by increasing the number M of gate-selecting lines to decrease the number of bonding pads. However, if the number of the gate-selecting lines is increased, then the length of a short side of the chip is increased because the gate-selecting lines are elongated end to end of the chip and in parallel with the long side of the chip. Therefore, it is required that the number of gate-selecting lines is determined so that the bonding pads may be arrayed in one line and the number M of the gate-selecting lines becomes as small as possible.
In a light-emitting thyristor matrix array comprising N (N is an integer≧2) three-terminal light-emitting thyristors arrayed in one line, cathodes or anodes of the N light-emitting thyristors are connected to a common terminal, M (M is an integer≧2) gate-selecting lines are provided, the gate of kth light-emitting thyristor is connected to ith [i={(k−1) MOD M}+1] gate-selecting line G
i
, wherein “(k−1)MOD M” means a remainder when (k−1) is divided by M, and the anode or cathode (which is not connected to the common terminal) of the kth light-emitting thyristor is connected to jth [j={(k−i)/M}+1] anode terminal A
j
or cathode terminal K
j
.
In this case, the number M of the gate-selecting lines is selected so as to satisfy the relationship of L/{(N/M)+M}>p, wherein “L” is a length of the long side of the chip, and “p” is a critical value of array pitch of the bonding pads. The value of “p” may be small when a high accuracy wire bonding machine is used, but too small value make an operation time longer. Therefore, the value of “p” is practically around 75 &mgr;m.
According to the present invention, the anodes or cathodes may be connected to selecting lines. In this case, cathodes or anodes of the N light-emitting thyristors are connected to a common terminal, M (M is an integer≧2) anode-selecting lines or cathode-selecting lines are provided, the anode or cathode which is not connected to the common terminal of the kth light-emitting thyristor is connected to ith [i={(k−1)MOD M}+1] anode-selecting line A
i
or cathode-selecting lines K
i
, and the gate of the kth light-emitting thyristor is connected to jth [j={(k−i)/M}+1] gate terminal G
j
.
A light-emitting thyristor matrix array chip including a plurality of bonding pads arrayed in one line in parallel with the long side of the chip is positioned adjacent to a driver IC. The terminal of the light-emitting thyristor matrix array chip are connected through bonding wires directly to that of the driver IC.
In the structure such that the matrix array chip and the driver IC are connected directly by bonding wires, the array pitch of the bonding pads of the chip is to be
Kusuda Yukihisa
Ohno Seiji
Flynn Nathan J.
Mondt Johannes P.
Nippon Sheet Glass Co. Ltd.
RatnerPrestia
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