Optics: measuring and testing – By alignment in lateral direction
Reexamination Certificate
1996-09-25
2001-01-09
Kim, Robert (Department: 2877)
Optics: measuring and testing
By alignment in lateral direction
C356S401000
Reexamination Certificate
active
06172757
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates generally to processing semiconductor wafers, and in particular, to an apparatus and a method for sensing the level or tilt of wafers on probing stations.
(2) Description of the Related Art
In the manufacture of semiconductor wafers, the latter are probed and tested many times and for many different purposes. Probing usually means contacting or touching a particular object with a probe, or a long and thin implement, such as a wire . In order to touch an object assuredly, it is necessary that that object be secured firmly in place. Thus, in probing wafers, the wafer is first mounted on a chuck or table to hold it in a fixed position. The means for holding the wafer on the table may be accomplished in various ways, of which applying vacuum through holes leading to the table surface is well known in the art. The wafer is so held to the table firmly. The regions or features to be probed on the wafer surface are next aligned with respect to the probing elements before they are actually contacted by the probes. While alignment techniques in prior art have been adequate up until recently, they are found to be more and more wanting with the much finer features of the recent sub-micron very and ultra large scale integrated (VLSI and ULSI) technologies. This is because of the effect that tilt and the degree of planarity of the object to be probed or tested have on the alignment with respect to the probes. Prior art does not address the problem of tilt as this invention does as disclosed further.
Alignment, that is, correct spatial relationship of the probes with respect to particular features will depend upon the object that is being probed and tested. For example, in probing for dopant profiles in semiconductor structures, the whole wafer is aligned to perform a two-point resistance measurement of the area of interest on the wafer surface following the conventional Spreading Resistance Probe (SRP) method. (See U.S. Pat. No. 5,347,226). On the other hand if probing is performed for electrically testing integrated circuit chips, then the leads of each chip is aligned precisely with respect to the probe elements of the tester as explained in U.S. Pat. No. 5,481,202. In either case, alignment will not be precise unless, in addition to the two-dimensional spatial relationship with respect to the features, the third dimension, namely, the height of probes above the features is also well established.
To show the influence of tilt on probing measurements by way of an example, consider FIGS.
1
a
-
1
c
of prior art. In FIG.
1
a
, surface (
10
) having features (
21
)-(
27
) is inclined at an arbitrary angle a in the xz-plane. Probes (
31
)-(
37
) in a plane are aligned horizontally above features (
21
)-(
27
) as shown in FIG.
1
a
. Though probes (
31
), (
32
) and (
33
) are aligned in the yz-plane as shown in FIG.
1
b
, not all the remaining probes, e.g., (
34
) and (
37
), See FIG.
1
c
, reach and contact the corresponding features (
24
) and (
27
) due to tilt. In the absence of full contact with all probes, the test results will be erroneous, which in turn, will result in yield loss. In prior art, it is possible to adjust or extend all probes by a certain amount so as to be able to reach those features farthest down on the inclined surface (
10
). However, it will be appreciated by those skilled in the art that in that case, probes contacting features at higher elevations will be buckled and some, in fact, will be broken because of the contact forces that bear on them. Thus, using this example as a case in point, it is evident that information on tilt as well as the dimensions of the features are important for accurate probing. To accomplish this in the general case where probing is not only limited to probes as shown in FIG.
1
a
-
1
c
, a better mechanism is needed to be able to view the probing field better, and measure spatial relationships such as tilt in a more reliable manner.
Manual alignment, by human operator using a microscope and manual mechanical adjustments, has been the traditional method used. Usually a visual inspection of the wafer or the chip to be probed is first performed. The scan is typically done optically, with an operator or computer visually checking for any defects. Then the probes are aligned with respect to the features to be probed and tested. Because separate machines are required to accomplish the scanning step and the alignment/testing step, the article to be tested often slips or alters its position slightly before or during testing process. In order to address this problem, U.S. Pat. No. 5,283,141 mentioned above discloses an apparatus in which both the scanning and alignment/testing are accomplished in the same location. However, there is no additional provision for adjusting the probes for vertical alignment.
Automatic alignment methods have also been developed such as for wafer steppers, which require no human intervention. Equipment that perform alignment not for the whole wafer, but only portions thereof, are known in the field as steppers and are mostly used in conducting lithographic processes in the manufacture of integrated circuits (IC). For example, in forming circuits on an IC wafer, circuit patterns are projected through a mask onto a silicon wafer. Because it is impractically complex and expensive to produce a lens capable of projecting a mask over an entire wafer of 100 mm or larger, steppers have been designed to step and repeat across the wafer the pattern field to ve projected. With smaller working area than the whole wafer, therefore, the steppers can provide better alignment and hence better registration of patterns on the wafer surface. Microlithography of the ULSI era of today, however, requires extreme accuracy and precision in the projection of patterns on wafers without any distortion. Distortion can easily be introduced depending upon the particular area on the wafer and also depending upon the unevenness (tilt) with which the wafer is being held on its holder. Even though prior art provides a smaller area to work with the steppers, it has been observed in the present state of the manufacturing of wafers that there is a need to be able to vary further the area under consideration in order to provide improved alignment capability.
Common to different types of alignment including those described above (namely, alignment for dopant profiles in a semiconductor structure, for projecting patterns on a wafer, or for electrical testing of IC chips) is the problem of determining precisely the location of features to be probed. As described earlier in reference to with FIGS.
1
a
-
1
c
, in addition to the two-dimensional topographical information, a third dimension on the tilt of the features to be probed is also needed. Furthermore, in order to obtain such information at a particular location on the wafer, there is a need for a level sensor with variable area viewing capability. The present invention discloses an improved level sensor apparatus capable of obtaining said information at different areas, including chip sites, on a wafer.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide an improved level sensor apparatus for measuring, on wafers, location and tilt (relative to the horizontal) of features in different areas in general, and on chip sites, in particular.
It is another object of this invention to provide an improved level sensor apparatus with an adjustable zoom lens for varying the depth of focus in measuring tilt of features in different areas and on chip sites on wafers.
It is still another object of this invention to provide an improved level sensor apparatus with variable viewing field for measuring location and tilt of features in different areas and on chip sites on wafers.
It is yet another object of this invention to provide an improved method for measuring on wafers location and tilt of features in different areas in general, and on chip sites, in particular.
In accordance with the afore-mentioned objects,
Ackerman Stephen B.
Kim Robert
Saile George O.
Vanguard International Semiconductor Corporation
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