Level translation circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307443, 307451, 307576, H03K 19092, H03K 1716, H03K 17687

Patent

active

047913231

ABSTRACT:
A TTL/CMOS interface circuit comprised entirely of CMOS components. An input gain stage comprised of transistors of a single conductivity type is provided whose gain is established by the ratio of the geometric size of the transistors. In the preferred embodiment of the present invention, the input gain stage is comprised of N channel transistors to a void process related mismatches. An inverter stage has a switching threshold set to optimally operate with the output of the input gain stage. The voltage at the inverter stage is tied to the power supply voltage to supply an upper voltage limit. In order to provide for zero power operation for input signals close the value of the supply voltage, a transistor is provided to cut current flow in the input stage for input signals within a threshold voltage of the supply voltage. The present circuit may also be utilized as to allow zero power operation for input signals close to ground.

REFERENCES:
patent: 4258272 (1981-03-01), Huang
patent: 4612461 (1986-09-01), Sood

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