Level shifting circuit

Details Level shifting circuit Level shifting circuit

2002-10-10

2003-12-30

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

Reexamination Certificate

active

06670841

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a level shifting circuit for converting a logical level.
2. Description of Related Art
FIG. 10
is a circuit diagram to show a conventional level shifting circuit. In a semiconductor device using two types of voltage sources, a low voltage source (VCCL) and a high voltage source (VCCH), the level shifting circuit serves as a circuit which converts the logical level of the voltage VCCL into the logical level of the voltage VCCH (VCCL<VCCH). In
FIG. 10
, reference sign IN_L denotes an input signal having the logical level of the voltage VCCL, sign OUT_H denotes an output signal having the logical level of the voltage VCCH, signs INV
1001
_L and INV
1002
_L denote inverters operating by the low voltage source (VCCL), sign INV
1003
denotes an inverter operating by the high voltage source (VCCH), signs MP
1001
and MP
1002
denote high-voltage P-type transistors and signs MN
1001
and MN
1002
denote high-voltage N-type transistors.
FIG. 11
is a waveform chart to show an operation of the conventional level shifting circuit.
Next, an operation will be discussed.
The operation of the level shifting circuit shown in
FIG. 10
will be discussed below, referring to the waveform chart of FIG.
11
. In the following discussion, the logic High level of the voltage VCCL is represented as “H_l” level, the logic High level of the voltage VCCH is represented as “H_h” level and the logic Low level (0 V) of these voltages are represented as “L”.
In a state where the input signal IN_L is stationary at the “L” level, a node N
1001
has the “H_l” level and a node N
1002
has the “L” level, and the high-voltage N-type transistor MN
1001
is in an ON state and the high-voltage N-type transistor MN
1002
is in an OFF state. Further, a node N
1003
has the “L” level and a node N
1004
has the “H_h” level, and the high-voltage P-type transistor MP
1001
is in the OFF state and the high-voltage P-type transistor MP
1002
is in the ON state. The output signal OUT_H has the “L” level.
When the input signal IN_L changes from the “L” level to the “H_l” level (t
0
of FIG.
11
), the node N
1001
comes into the “L” level and the node N
1002
comes into the “H_l” level by the operations of the inverters INV
1001
_L and INV
1002
_L (
1
,
2
of
FIG. 11
) and the high-voltage N-type transistor MN
1001
comes into the OFF state and the high-voltage N-type transistor MN
1002
comes into the ON state. At this time, since the high-voltage P-type transistor MP
1002
remains in the ON state, the potential of the node N
1004
falls to a voltage value V
0
obtained by dividing the voltage VCCH by the ON-resistance of the high-voltage P-type transistor MP
1002
and the ON-resistance of the high-voltage N-type transistor MN
1002
(
3
of FIG.
11
). When the potential of the node N
1064
becomes VCCH−VthP (VthP represents a threshold voltage of the high-voltage P-type transistor) or lower, the high-voltage P-type transistor MP
1001
comes into the ON state and the node N
1003
is charged up to the voltage VCCH (
4
of
FIG. 11
) and when the potential of the node N
1004
becomes the threshold voltage of the inverter INV
1003
or lower, the out put signal OUT_H becomes “H_h” level (
5
of FIG.
11
). Further; since the node N
1003
is charged up to the voltage VCCH, the high-voltage P-type transistor MP
1002
comes into the OFF state and the node N
1004
is completely discharged to 0 V (
6
of FIG.
11
).
When the input signal IN_L changes from the “H_l” level to the “L” level (t
1
of FIG.
11
), a series of operation is performed, almost like the above, where the node N
1001
changes to the “H_l” level and the node N
1002
changes to the “L” level (
11
,
12
of FIG.
11
), the high-voltage N-type transistor MN
1001
comes into the ON state and the high-voltage N-type transistor MN
1002
comes into the OFF state, the potential of the node N
1003
falls to V
0
(
13
of. FIG.
11
), the high-voltage P-type transistor MP
1002
comes into the ON state, the potential of the node N
1004
rises up to the voltage VCCH (
14
of FIG.
11
), and then when the potential of the node N
1004
becomes the threshold voltage of the inverter INV
1003
or higher, the output signal OUT_H changes to the “L” level: (
15
of
FIG. 11
) and the potential of the node N
1003
changes to 0 V (
16
of FIG.
11
).
As discussed above, there is a case in the conventional level shifting circuit, where the high-voltage P-type transistor MP
1001
and the high-voltage N-type transistor MN
1001
come into the ON state at the same time or where the high-voltage P-type transistor MP
1002
and the high-voltage N-type transistor MN
1002
come into the ON state at the same time (
3
,
13
of FIG.
11
), and the voltage V
0
of the node N
1001
or the node N
1002
at that time should be VCCH−VthP or lower. Assuming that the ON-resistance of the high-voltage P-type transistor is RonP and the ON-resistance of the high-voltage N-type transistor is RonN, since V
0
=VCCH*RonN/(RonP+RonN), it is necessary to satisfy a relation RonP>RonN in order to set V
0
to a low value to some degree. Further, assuming that the channel width of a transistor is W and the channel length thereof is L, since the ON-resistance thereof is in proportion to L/W, it is necessary to set the channel width W smaller and/or the channel length L larger in order to increase the ON-resistance and it is necessary to set the channel width W larger and/or the channel length L smaller in order to decrease the ON-resistance.
With refinement of semiconductor integrated circuits, a power supply voltage used in a semiconductor chip decreases and a difference between this power supply voltage and a power supply voltage for external output signals of the semiconductor chip is widened. The above discussed level shifting circuit is also used for, e.g., converting a logical signal of the low voltage source (VCCL) into a logical signal of the high voltage source (VCCH) for external output inside the semiconductor chip. Since a low-voltage transistor used in a circuit operating by the low voltage source (VCCL) is designed to perform an optimum operation with a low voltage and has a low breakdown voltage, there is a possibility that the low-voltage transistor may be broken when a high voltage is applied thereto. For this reason, a high-voltage transistor having a high breakdown voltage is used for a level shifting circuit connected to a high voltage source (VCCH). A threshold voltage of the high-voltage transistor is higher than that of a low-voltage transistor. When the voltage VCCL of the low voltage source becomes lower, the difference between the voltage VCCL and the threshold voltage (VthN) of the high-voltage N-type transistors MN
1001
and MN
1002
becomes smaller, and this leads to a problem that the high-voltage N-type transistor MN
1001
or the MN
1002
does not come into the ON state even if the node N
1001
or the node N
1002
becomes “H_l” level respectively.
Further, even when the voltage VCCL is equal to the threshold voltage (VthN) of the high-voltage N-type transistors MN
1001
and MN
1002
or higher, since a gate source voltage (VCCL) at the time when;the high-voltage N-type transistors MN
1001
and MN
1002
are in the ON state is lower than a gate-source voltage (−VCCH) at the time when the high-voltage P-type transistors MP
1001
and MP
1002
are in the ON state, the ON-resistance RonN of the high-voltage N-type transistor is hard to reduce even if L/W of the high-voltage N-type transistors MN
1001
and MN
1002
is made smaller, and this tendency is accelerated as the difference between the voltage VCCH and the voltage VCCL becomes larger. Therefore, in order to satisfy the relation RonP>RonN, it is necessary to set the ON-resistance RonP extremely high. Since the nodes N
1001
and N
1002
are charged by the high-voltage P-type transistors MP
1001
and MP
1002
(
4
,
14
of FIG.
11
), however, the charging speed becomes lower when the ON-resistance RonP is extrem

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