Level shifting BIMOS integrated circuit

Details Level shifting BIMOS integrated circuit Level shifting BIMOS integrated circuit

1984-07-30

1987-02-24

Edlow, Martin H.

357 42, 357 48, H01L 2702, H01L 2704

Patent

active

046461248

ABSTRACT:
An integrated circuit has small signal MOS logic transistors formed in an N-type basket which basket itself is formed in an N-type epitaxial pocket that is defined by an enclosing P-type isolation wall. In a second epitaxial pocket a relatively high-current carrying bipolar transistor is formed. The MOS containing N-type basket is tied to one DC voltage which the substrate and isolation walls are connected to a lower level DC voltage. Substrate currents that are caused by the high current in the bipolar transistor are prevented by the N-type basket from inducing voltage changes in the MOS transistors.

REFERENCES:
patent: 4032372 (1977-06-01), Vora
patent: 4161417 (1979-07-01), Yim et al.
patent: 4225877 (1980-09-01), Miles et al.
patent: 4403395 (1983-09-01), Curran
patent: 4458158 (1984-07-01), Mayrand

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