Level shifter for multiple supply voltage circuitry

Details Level shifter for multiple supply voltage circuitry Level shifter for multiple supply voltage circuitry

1999-12-28

2001-09-11

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C327S259000, C326S081000

Reexamination Certificate

active

06288591

ABSTRACT:

TECHNICAL FIELD
The present invention relates in general to multiple supply voltage integrated circuits. More in particular, the present invention relates to interface circuitry between networks biased at different voltage levels.
BACKGROUND OF THE INVENTION
Many electrical circuits are composed of multiple functional units, in which the supply voltage of each functional unit is adjusted in order to minimize the overall system-level power consumption. To interface between those blocks, a voltage level shifter is employed to switch between the voltage levels of the respective functional blocks. Although level shifters can shift from low to high voltage or from high to low voltage, the following discussion focuses on the former type.
It should be appreciated that the terms “low voltage” and “high voltage” are used herein in their relative senses without limiting them to actual values, that is, “low” is simply low relative to “high.” For example, a “low” voltage may have a voltage level at logic low of less than 0.7 V and a voltage level at logic high of 2.5V while a “high” voltage may have a voltage level at logic 0 of less than 1.0V and a voltage level at logic high of greater than 5V. Other values are certainly contemplated and are within the general scope of the present invention.
In order to simplify the system layout, a level shifter can be thought of as divided into two parts: a sender and a receiver. The sender is the input section of the level shifter and works at low voltage and the receiver is the output section and works at high voltage. In this way, suppose a block A works with low voltage, and a block B works with high voltage. The layout or block A would include the sender portion of a level shifter and the layout or block B would include the receiver portion of the level shifter.
FIG. 1
shows a well known circuit implementation of a voltage level shifter
10
. The level shifter
10
includes an input terminal
11
that receives a low voltage input signal INP and an input inverter
12
that inverts the input signal to produce a complementary input signal INP_INV. Respectively connected to the input terminal
11
and the output of the input inverter
12
are gate terminals of first and second NMOS transistors MN
1
, MN
2
, both of which have source terminals coupled to ground. The second NMOS transistor also has a drain terminal that acts as an output terminal
13
. Respectively connected in series to drain terminals of the first and second NMOS transistors MN
1
, NN
2
are drain terminals of cross-coupled first and second PMOS transistors MP
1
, MP
2
, both of which have source terminals coupled to a high voltage supply reference. The first and second PMOS transistors are cross-coupled in that a gate terminal of the first PMOS transistor MP
1
is coupled to the drain terminal of the second PMOS transistor MP
2
, which has a gate terminal coupled to the drain terminal of the first PMOS transistor MP
1
. The first and second NMOS and PMOS transistors MN
1
, MN
2
, MP
1
, MP
2
together comprise a level shifting stage
14
. The capacitances C
1
, C
2
shown in
FIG. 1
are wire capacitances of the line connecting the input node to the first NMOS transistor MN
1
and the line connecting the input inverter
12
to the second NMOS transistor MN
2
, respectively.
The level shifter
10
converts the low voltage input signal INP at the input node
11
to a high voltage output signal OUT at the output node
13
as follows. When the input signal is logic low, the first NMOS transistor MN
1
is “off” and the second NMOS transistor MN
2
is “on” via the input inverter
12
. As a result, the second NMOS transistor electrically connects the output node
13
to ground which drives the output signal OUT to logic low. Further, the logic low output signal OUT turns “on” the first PMOS transistor which provides the high voltage supply reference to the gate terminal of the second PMOS transistor, which thereby is held “off.”
When the input signal INP goes high, the first NMOS transistor MN
1
is turned “on” and the second NMOS transistor MN
2
is turned “off.” Turning “on” the first NMOS transistor electrically connects to ground the gate terminal of the second PMOS transistor MP
2
, which thereby is turned “on” and provides the high voltage supply reference to the output node
13
.
It will be appreciated that the first NMOS transistor MN
1
will turn “on” before the second NMOS transistor MN
2
will turn “off” because of the delay introduced by the input inverter
12
. This causes a short circuit current to flow between the high voltage supply reference and ground via the NMOS and PMOS transistors MN
1
, MP
1
. Because the first NMOS transistor MN
1
is stronger than the first PMOS transistor MP
1
, the second PMOS transistor MP
2
will be switched “on”, causing a second short current to flow via the second NMOS and PMOS transistors MN
2
, MP
2
. These short circuit currents flow until the second NMOS transistor MN
2
is turned “off” by the input inverter
12
, which allows the second PMOS transistor MP
2
to turn “off” the first PMOS transistor MP
1
.
The mismatch in arrival times of the input signal INP and its complement INP_INV to the NMOS transistors MN
1
, MN
2
can be exacerbated by large wire capacitances C
1
, C
2
and by differences in the wire capacitances C
1
, C
2
. Such differences in the wire capacitances C
1
, C
2
can occur if the lines to the NMOS transistors MN
1
, MN
2
are wired differently. Such wire capacitances C
1
, C
2
typically do differ considerably because the sender and receiver portions of the level shifter typically are implemented in separate low voltage and high voltage wells of a semiconductor substrate. The bigger the capacitance values C
1
, C
2
, or their mismatch, or the eventual crosstalk effect, the longer the short circuit currents flow and more power is consumed. The added short circuit currents caused by the capacitive differences wastes energy and can cause serious power dissipation problems.
SUMMARY OF THE INVENTION
An embodiment of the invention is directed to a voltage level shifter and an associated level shifting method for shifting from a low voltage input signal to a high voltage output signal. The level shifter includes a voltage shifting stage having first and second control input nodes and an output node at which the output signal is produced based on control signals received at the control input nodes. The level shifter also includes first and second input inverters coupled in series between the input node and the first control input node; and a third input inverter coupled between the input node and the second control input node.
The second inverter can include complementary first and second transistors each with control terminals coupled to an output of the first inverter. The first transistor has a first terminal coupled to the input node and is structured to pass the input signal to the first control input node base, on a logic value of a signal output by the first inverter. The third inverter can include complementary third and fourth transistors each with control terminals coupled to the input node. The third transistor has a first terminal coupled to the output of the first inverter and is structured to pass the signal output by the first inverter to the second control input node based on a logic value of the input signal.


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patent: 5461333 (1995-10-01), Condon et al.
patent: 5495189 (1996-02-01), Choi
patent: 5510731 (1996-04-01), Dingwall
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patent: 5680064 (1997-10-01), Masaki et al.
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patent: 5952865 (1999-09-01), Rigazio
patent: 5973549 (1999-10-01), Yuh
patent: 6002290 (1999-12-01), Avery et al.
patent: 6133752 (2000-10-01), Kawagoe

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