Level-shifter circuit for high-speed low-power BiCMOS ECL to CMO

Details Level-shifter circuit for high-speed low-power BiCMOS ECL to CMO Level-shifter circuit for high-speed low-power BiCMOS ECL to CMO

1991-11-07

1992-12-22

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307446, 307451, 307455, H03K 19092, H03K 1902

Patent

active

051736241

ABSTRACT:
Input ECL level signals are received and converted into output CMOS level signals by input buffer (30). The input buffer (30) biased between first and second supply voltage (Vcc, Vee) and is comprised of three stages. The first stage (11A) consists of a conventional emitter-follower transistor (Q1) and a current-switch (13) connected in series. The input signal VIN at the ECL level is applied to the base of the emitter-follower transistor (Q1). The output signals (VA, VB) obtained therefrom drive a second stage which consists of an input buffer circuit (20), which supplies two pairs of output signals (V1) V2; V1', V2') for each phase. Each pair of output signals drives an output driver (31; 31') forming the third stage. The input buffer circuit (20) is composed of two NPN bipolar transistor (T1; T2) connected in an emitter-follower configuration forming two branches. In each branch, the emitter load consists of three FET devices: two PFETs (P1, P3; P2, P4 ) and one NFET (N1; N2) serially connected. The common node (E; F) between the PFETs in one branch, is cross-coupled to the gate electrode of the NFET (N2; N1) of the other branch. The gate electrode of the PFET (P1; P2) connected to the emitter of the bipolar transistor (T1; T2) in one branch is driven by the potential of the common node formed by the other PFET (P4, P3) and the NFET (N2; N1) in the other branch. The IN PHASE (VOUT) and OUT OF PHASE (VOUT) circuit output signals are available at the circuit output terminals (32; 32') of said output drivers (31; 31') at the CMOS levels.

REFERENCES:
patent: 4806799 (1989-02-01), Pelley et al.
patent: 4992681 (1991-02-01), Urakawa et al.
patent: 5068551 (1991-11-01), Bosnyak
patent: 5075578 (1991-12-01), Wendell
patent: 5103121 (1992-04-01), Wendell et al.
IEEE JSSC, vol. 24, No. 4, Aug. 1989, "An 8-ns 256K BiCMOS RAM", by N. Tamba et al.

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