Level shifter

Details Level shifter Level shifter

2001-03-05

2002-05-07

Nguyen, Chanh (Department: 2675)

Computer graphics processing and selective visual display system

Plural physical display element control system

Display elements arranged in matrix

C345S092000

Reexamination Certificate

active

06384808

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a level shifter that is employed in a driver circuit of an image display device (active matrix image display device) for displaying information such as an image by means of switching elements and pixels arranged in matrix.
2. Description of the Related Art
In recent years, the fining of a technique in manufacturing semiconductors is advancing. Further, because of the popularized electronic equipment such as a portable equipment which demands low consumption power, the LSI that is used in these equipments has become 3.3 V, that is, a 3.3 V low power source voltage drive has become the mainstream. On the other hand, in a liquid crystal display, which is recently in high demand for its use as a monitor of a portable terminal, computer, etc., a liquid crystal drive is conducted by a 10 to 20 V of voltage amplitude signal. Thus, it has become necessary to provide at least a circuit portion that operates at a high power source voltage corresponding to the voltage amplitude of the driver circuit thereof.
Therefore, between the low voltage amplitude signal of a controller LSI and the high voltage amplitude signal that is necessary to drive the liquid crystal display, a level shifter for performing a voltage amplitude conversion becomes indispensable.
A conventional level shifter that is generally used is shown in FIG.
23
. This level shifter converts a signal having a 0 to VDD
1
(>0, for example 5 V) voltage amplitude to a signal having a 0 to VDD
2
(>VDD
1
, for example 10 V) voltage amplitude. That is, it is a level shifter which shifts a high electric potential side while a low electric potential side is fixed. The structure thereof is as follows. A source of a P channel MOS transistor (hereinafter abbreviated as PMOST)
101
and a source of a PMOST
102
are each connected to a power source VDD
2
, and a drain of the PMOST
101
is connected to a source of a PMOST
103
while a drain of the PMOST
102
is connected to a source of a PMOST
104
, respectively. Further, a drain of the PMOST
103
is connected to a gate of the PMOST
102
and to a drain of an N channel MOS transistor (hereinafter abbreviated as NMOST)
105
, and drain of the PMOST
104
is connected to a gate of the PMOST
101
and to a drain of an NMOST
106
. A source of the NMOST
105
and a source of the NMOST
106
are connected to a GND (0 V). Furthermore, an input signal (IN) is fed to the gate of the PMOST
103
and that of the NMOST
105
while an inverted input signal (/IN) of the input signal (IN) is fed to the gate of the PMOST
104
and that of the NMOST
106
, respectively, to thereby extract an output signal (OUT) from the drain of the NMOST
106
. It is to be noted that an inverted output signal (/OUT) of the above output signal can be extracted from the drain of the NMOST
105
.
Note that in regards to the power source voltage, the VDD# of the power source is expressed as power source VDD# (where # denotes a number) throughout the present specification. Further, GND, VDD
1
, VDD
2
, VDD
3
, and VDD
4
will be taken as the 5 kinds of power source voltage and their relationship according to the voltage level satisfies VDD
4
<VDD
3
<GND<VDD
1
<VDD
2
. However, the voltage of GND is set to 0 V in order to simplify the explanation.
A basic operation of the example of the conventional level shifter will be explained next. When the electric potential of the input signal (IN) is “Hi” of VDD
1
, then the NMOST
105
is turned ON and the PMOST
103
is turned OFF, whereby the electric potential “Lo” of GND is fed to the gate of the PMOST
102
to thereby turn the PMOST
102
ON. On the other hand, the electric potential of the inverted input signal (/IN) is “Lo” of GND, and thus the NMOST
106
is turned OFF while the PMOST
104
is turned ON. Therefore, both PMOSTs
102
and
104
are turned ON and the electric potential is shifted, whereby the output signal (OUT) becomes “Hi” of VDD
2
. It is to be noted that the PMOST
101
becomes OFF to thereby ensure that the gate of the PMOST
102
is held at the “Lo” level of GND by the electric potential.
When the electric potential of the input signal (IN) is “Lo” of GND, the level shifter shown in
FIG. 23
takes a symmetrical structure. Thus, similar to the above, it can be comprehended that the electric potential “Lo” of GND (0 V) is outputted from the output terminal (OUT).
Accordingly, a signal having a voltage amplitude of 0 to VDD
1
is thus converted to a signal having a voltage amplitude of 0 to VDD
2
.
Next, an example of a conventional level shifter which shifts the low electric potential side while the high electric potential side is fixed is shown in FIG.
24
. This level shifter converts a signal having a VDD
3
(<0) to 0 voltage amplitude to a signal having a VDD
4
(<VDD
3
) to 0 voltage amplitude. The structure thereof is as follows. A source of an NMOST
107
and a source of an NMOST
108
are each connected to the power source VDD
4
, and a drain of the NMOST
107
is connected to a source of an NMOST
109
while a drain of the NMOST
108
is connected to a source of an NMOST
110
, respectively. Further, a drain of the NMOST
109
is connected to a gate of the NMOST
108
and to a drain of a PMOST
111
, and drain of the NMOST
110
is connected to a gate of the NMOST
107
and to a drain of a PMOST
112
. A source of the PMOST
111
and a source of the PMOST
112
are connected to the GND (0 V). Furthermore, an input signal (IN) is fed to the gate of the NMOST
109
and that of the PMOST
111
while an inverted input signal (/IN) of the input signal (IN) is fed to the gate of the NMOST
110
and that of the PMOST
112
, respectively, to thereby extract an output signal (OUT) from the drain of the PMOST
112
. It is to be noted that an inverted output signal (/OUT) of the above output signal (OUT) can be extracted from the drain of the PMOST
111
.
A basic operation of the example of the conventional level shifter shown in
FIG. 24
will be explained next. When the electric potential of the input signal (IN) is “Lo” of VDD
3
, then the PMOST
111
is turned ON and the NMOST
109
is turned OFF, whereby the electric potential “Hi” of GND is fed to the gate of the NMOST
108
to thereby turn the NMOST
108
ON. On the other hand, the electric potential of the inverted input signal (/IN) is “Hi” of GND, and thus the PMOST
112
is turned OFF while the NMOST
110
is turned ON. Therefore, both NMOSTs
108
and
110
are turned ON and the electric potential is shifted, whereby the output signal (OUT) becomes “Lo” of VDD
4
. It is to be noted that the NMOST
107
becomes OFF to thereby ensure that the gate of the NMOST
108
is held at the “Hi” level of GND by the electric potential.
When the electric potential of the input signal (IN) is “Hi” of GND, the level shifter shown in
FIG. 24
takes a symmetrical structure. Thus, similar to the above, it can be comprehended that the electric potential “Hi” of GND is outputted from the output terminal (OUT).
Accordingly, the signal having a voltage amplitude of VDD
3
to 0 is thus converted to a signal having a voltage amplitude of VDD
4
to 0.
The above described example of the conventional level shifter can comparatively easily perform level conversion between voltage amplitudes having a small difference. However, as the difference between the voltage amplitudes becomes large, it becomes more difficult for the level shifter to perform level conversion, resulting in the occurrence of problems. These problems will be explained in the following.
Although the basic operation of the exemplified conventional level shifter was simply explained in the above, precisely, points such as to perform an operation or not or the operating time are determined depending on the voltage amplitude to be converted, the characteristic of the transistor, and the like. In the level shifter shown in
FIG. 23
, for example, let's assume that VDD
1
=5 V, VDD
2
=15 V, a threshold voltage of the

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