Level shifter

Details Level shifter Level shifter

2000-02-29

2001-08-07

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C327S433000

Reexamination Certificate

active

06271707

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to electronics, in general, and to level shifters, in particular.
BACKGROUND OF THE INVENTION
Transistors used in integrated circuits typically operate between a supply voltage and ground potential. One common supply voltage used in the past has been 5 volts. More recently, circuit devices operating with lower voltage requirements, for example, 3.3 volts, 2.75 volts, and 2.5 volts, have been developed. Future circuits may use even lower voltage supplies. The need for lower voltage supplies results from a number of factors. A lower voltage typically means that less power is consumed by the circuit, which is especially important in battery-operated devices such as cellular telephones. Secondly, submicron Complimentary Metal Oxide Semiconductor (CMOS) or Bipolar CMOS (BiCMOS) processes with increasingly smaller physical dimensions need to operate at lower supply voltages because of reliability concerns, including the hot electron effect and circuit current leakage. Unfortunately, in many instances, higher supply voltages are still required at the interface levels. Thus, level shifters are needed to translate from one voltage level to a higher, or lower, voltage level. Many of these lower voltage integrated circuits have and will continue to interface with conventional higher voltage integrated circuits and with circuits of different voltage levels.
Buffer circuits or level shifters for converting a signal having an input voltage level into a signal having a different predetermined voltage level are commonly used as input buffers in semiconductor devices and have been designed to interface between circuitry of two different voltage levels. Difficulties can arise, however, when designing such buffer circuits that include submicron N-channel Metal Oxide Semiconductors (NMOS) field effect transistors (FETs). For example, in many instances the maximum voltage permitted across any pair of terminals of submicron NMOS transistors is about 3.5 volts. As is known in the art, keeping the voltage across a pair of submicron NMOS terminals below about 3.5 volts in a 0.4 &mgr;m CMOS/BiCMOS process for example, generally prevents the occurrence of the hot electron effect, which can degrade the NMOS transistors over time and eventually cause circuit failure.
Accordingly, a need exists for level shifter capable of translating a lower binary voltage signal level to a higher binary voltage signal level. It is desired that the level shifter be configured using CMOS and NPN bipolar devices and that all NMOS transistors included in the level shifter circuitry have voltages at or below a voltage of about 3.5 volts to prevent the potential occurrence of hot electron effects. It is also desired that the quiescent current flowing through the level shifter, for example, during a battery save mode, be relatively low, preferably less than 1 microAmpere (uA) and, most preferably on the order of about a few hundred nanoAmperes (nA).


REFERENCES:
patent: 4220873 (1980-09-01), Giordano
patent: 4220877 (1980-09-01), Giordano
patent: 5504450 (1996-04-01), McPartland
patent: 5852383 (1998-12-01), Rombach
patent: 6137339 (2000-10-01), Kibar et al.

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