Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
2002-05-30
2004-04-06
Nguyen, Long (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S427000, C326S068000, C326S081000
Reexamination Certificate
active
06717452
ABSTRACT:
TECHNICAL FIELD
The present invention relates in general to data processing systems, and in particular, to the transfer of data signals within integrated circuitry.
BACKGROUND INFORMATION
Level shifting receivers translate signals between two voltage supply domains. For example, receivers may translate signals originating from an integrated circuit operating under a lower supply voltage (e.g., 1.8 volts (V)) to an integrated circuit operating with a higher supply voltage (e.g., 2.5 V). Prior art circuits have also been designed that permit the isolation of the receiver from the removal of the driver supply voltage.
Referring to
FIG. 3
, there is illustrated prior art level shifter
100
, wherein the low-voltage supply is designated as Vdd and the high voltage supply is designated as Vdd_H. The data in input signal is buffered by inverters operating under the lower supply voltage Vdd. The first inverter is comprised of NFET (N-channel field effect transistor)
301
and PFET(P-channel FET)
302
, while the second inverter is comprised of PFET
303
and NFET
304
. The complementary outputs of these two inverters are driven to pull-down NFETs
305
and
308
with cross-coupled PFETs
306
and
307
. This prior art circuit has the disadvantage that it does not preserve valid signal levels in the event that the voltage Vdd is disabled, i.e., either forced to the same potential as the ground or allowed to degrade over time to the ground potential (for example, portable electronic devices employ nonpersisent power supply domains where the voltage supply is removed from the circuitry to preserve battery power). In particular, as the supply degrades toward ground, the nodes at the drain of the cross-coupled PFETs will both rise up to within a threshold voltage of the high voltage supply, Vdd_H.
In addition, as the voltage Vdd is degrading toward ground, one cannot be certain that the inverters powered by Vdd will maintain their relative order: whichever signal amongst the output of the first inverter, formed by devices
301
and
302
, and the output of the second inverter, formed by devices
303
and
304
, which was initially higher in voltage may, as the supply degrades, become lower in voltage. This change in the relative maximum voltage signal increases power consumption and may cause the output DATA OUT to change state.
When the level shifter is used in an environment where the low voltage supply can be removed, for instance to save power, the level shifter may be augmented with isolation NFETs, such as NFETs
410
and
412
shown in the level shifter
400
of FIG.
4
. Such isolation NFETs help prevent transient events during the removal of the Vdd supply from affecting the state of the level shifter. Devices
401
-
404
operate similarly to devices
301
-
304
; device
409
operates similarly to device
305
; devices
406
-
407
operate similarly to devices
306
-
307
; and device
411
operates similarly to device
308
. Prior to the removal of Vdd, the HOLD signal is driven low to isolate the shifter
400
. To hold the state of the various signals within the level shifter
400
, the cross-coupled NFETs
405
and
408
are added. Thus when Vdd is removed, the state of the level shifter
400
when the HOLD signal is removed is maintained. However, the cascaded NFETs
409
/
410
and
411
/
412
limit the performance of the level shifter, primarily limiting the voltage gain range of the output of the shifter. There are two major problems with this prior art circuit due to the cascaded transistors: the cascaded transistors limit the difference between the supplies Vdd_H and Vdd, and because the transistors are cascaded, they must be large which increases circuit area and power consumption.
Thus, there is a need in the art for a level shifter that overcomes the aforementioned deficiencies, thus providing a gain in the active voltage range of the Vdd supply.
SUMMARY OF THE INVENTION
The present invention addresses the foregoing needs by allowing a significantly greater voltage difference between the low and high level power supplies in the implementation of level shifters, and supports the removal of the driver power supply from the low level circuitry while maintaining the integrity of the data signal at the high level circuitry output side. This is accomplished in part by eliminating the cascaded devices in the level shifter.
One embodiment of the present invention is a level shifter comprising a data input node, a first inverter having its input connected to the data input node, a second inverter connected to an output of the first inverter, a data output node, a latch having its output connected to the data output node, a first NFET connected between an input of the latch and a ground potential, and having its gate electrode connected to an output of the second inverter, and a second NFET connected between the data output node and the ground potential, and having its gate electrode connected to the output of the first inverter.
Another embodiment of the present invention is as a data processing system comprising a microprocessor and accompanying circuitry outputting data signals with a voltage swing magnitude of 1.8 volts, level shifter circuitry for converting the voltage swing magnitude of the data signals from 1.8 volts to 3.3 volts, and input/output (I/O) circuitry for receiving the data signals with the voltage swing magnitude of 3.3 volts.
Another embodiment of the present invention is as a level shifter comprising first circuitry for receiving a data signal having a voltage swing from ground to 1.8 volts, and second circuitry for converting the data signal to have a voltage swing from ground to 3.3 volts.
Another embodiment of the present invention is as a level shifter comprising a data input node, a first NOR gate coupled to the data input node, a second NOR gate coupled to an output of the first NOR gate, a storage cell coupled to an output of the second NOR gate, and a data output node coupled to an output of the storage cell.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.
REFERENCES:
patent: 5153451 (1992-10-01), Yamamura et al.
patent: 5324996 (1994-06-01), Mote, Jr.
patent: 5559996 (1996-09-01), Fujioka
patent: 5680064 (1997-10-01), Masaki et al.
patent: 5917339 (1999-06-01), Kim
Carpenter Gary Dale
Nowka Kevin John
International Business Machines - Corporation
Kordzik Kelly K.
Nguyen Long
Salys Casimer K.
Winstead Sechrest & Minick P.C.
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