Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With bootstrap circuit
Reexamination Certificate
1998-07-13
2001-03-27
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With bootstrap circuit
C327S534000, C327S543000, C365S189090
Reexamination Certificate
active
06208200
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a level shift circuit which converts or shifts a voltage level to a different voltage level.
2. Description of the Related Art
In a semiconductor memory device, for example, in a flash memory having a single power source, a level shift circuit for converting or shifting a voltage level of a signal from the level of an external power source voltage V
DD
such as 5V to a high voltage level of, for example, 12V to 20V generated by an internal voltage boosting circuit, is used for generating a boost voltage V
PP
during a writing and a deleting operation of the flash memory in order to supply to a control system for writing and deleting.
Two kinds of circuits are known as a level shift circuit in a flash memory having a single power source.
A first circuit is a CMOS type circuit using n channel MOS (NMOS) transistor and p channel MOS (PMOS) transistor which have a high voltage tolerance.
A second circuit is a charge pump type circuit using only a MOS transistor, which can be either NMOS transistor or a PMOS transistor.
FIG. 11
is a circuit diagram illustrating the configuration of a CMOS type level shift circuit, and
FIG. 12
shows input and output waveform characteristics of the circuit in FIG.
11
.
As shown in
FIG. 11
, the CMOS type level shift circuit
1
comprises a PMOS transistor PT
1
and an NMOS transistor NT
1
, and a PMOS transistor PT
2
and an NMOS transistor NT
2
which are connected in series between a high power source voltage V
pp
and the ground GND and an inverter INV
1
.
In this CMOS type level shift circuit, an input voltage V
in
having a level of a power source voltage V
dd
of, for example, 5V is supplied to a gate of the NMOS transistor NT
1
, is subjected to a level invention reaction in the inverter INV
1
, and is supplied to a gate of the NMOS transistor NT
2
at the ground level.
Along with this, the NMOS transistor NT
1
is turned on and the NMOS transistor NT
2
is turned off. Accordingly, the potential of a node ND
1
is drawn to the ground level. The ground level of the node ND
1
is supplied to the gate of the PMOS transistor PT
2
and the PMOS transistor PT
2
is turned on. As a result, the output node ND
2
is drawn to a high voltage V
pp
. That is, the input voltage V
in
at a V
dd
level is converted to a high voltage of 20V and output as V
out.
Contrary to this, when the input voltage V
in
is input at 0V, the NMOS transistor NT
1
is turned off and the NMOS transistor NT
2
is turned on. Accordingly, the output node ND
2
is drawn to the ground level. Namely, the input voltage V
in
at 0V is output as V
out
being unchanged at the ground level.
FIG. 13
is a circuit diagram showing the configuration of the charge pump type level shift circuit
10
, and
FIG. 14
shows the input and output waveform characteristics of the circuit in FIG.
13
.
This level shift circuit
10
comprises, as shown in
FIG. 13
, a depletion type NMOS transistor NTd
11
, NMOS transistors NT
11
, NT
12
and a capacitor C
11
used as a voltage boost element.
The depletion type NMOS transistor NTd
11
is connected between an input terminal T
in
and an output terminal T
out
, and a gate thereof is connected to an input terminal T
S1
of a signal SIG
1
.
The gate of the NMOS transistor NT
11
is connected to the output terminal T
out
, and the drain is connected to the supply line of the high voltage power source V
pp
, and the source is connected to the gate of the NMOS transistor NT
12
.
The drain of the NMOS transistor NT
12
is connected to its own gate and also to one electrode of the capacitor C
11
, and the source is connected to the output terminal T
out
.
The other electrode of the capacitor C
11
is connected to the input terminal T
CLK
of a clock signal CLK.
In this charge pump type level shift circuit
10
, when a signal SIG
1
is held at the source voltage level and the input voltage V
in
is set at the level of power source voltage V
dd
, the output voltage V
out
shifts to the level of approximate power source voltage V
dd
.
In this state, when the signal SIG
1
is lowered to 0V and the clock signal CLK is set to a high level which is the level of the power source voltage V
dd
. The voltage VNp of the node Np of the source side (the gate side of the NMOS transistor NT
12
) of the NMOS transistor NT
11
becomes in accordance with the formula:
VNp=V
out
−V
th(NT11)
+V
dd
where, V
th(NT11)
is a threshold voltage of the NMOS transistor NT
11
a.
As a result, the charge flows from the node Np through the NMOS transistor NT
12
to the output terminal T
out
and the output voltage V
out
rises a little.
In a balanced state, the voltage of the node Np rises up to the level expressed by the following formula:
VNp=V
out
+V
th(NT12)
.
Here, if the level V
CLK
of the clock signal CLK is switched to the ground level, the voltage of the node Np follows in accordance with the following formula:
VNp=V
out
+V
th(NT12)
−V
dd
.
Namely, the voltage of the node Np on the source side of the NMOS transistor NT
11
becomes lower than the output voltage V
out
.
As a result, the charge flows from the power source of the high voltage V
pp
through the NMOS transistor NT
11
to the node Np and the formula VNp=V
out
−V
th(NT11)
applies in the balanced state.
By repeating the above operation, the output voltage V
out
rises little by little/gradually each time when the clock signal CLK is switched from a high level to a low level.
The CMOS type level shift circuit shown in
FIG. 11
performs well at a low voltage because it does not suffer from a disadvantage of so called back-bias effect, and there is an advantage that the maximum voltage of the transistor therein is equal to the high voltage V
pp
. Also, the CMOS type level shift circuit performs well in a high speed operation and performs well with low power consumption.
However, it suffers from the disadvantage that the processing steps and the number of masks increase so that the cost rises.
The most advantageous point of the charge pump type level shift circuit such as shown in
FIG. 13
is that the cost can be low because neither a PMOS transistor nor an NMOS transistor having high voltage tolerance are used, so that less processing steps and masks are required.
Due to this advantage of low cost, the charge pump type level shift circuit is applied in the NAND type flash memory.
However, this circuit does not perform well in a low voltage operation because of the rise of the threshold voltage V
th
which is caused by a back-bias effect of the transistor therein. Also, the maximum voltage applied to the transistor in the circuit becomes as much as V
pp
+V
dd
, thus, it is difficult to design the processing of the transistor.
With the recent development in lowering voltages of power sources, especially of portable equipment, it is becoming difficult to meet the requirement of making the threshold voltage (V
th
) low in the NMOS transistor of the circuit shown in FIG.
13
. When the power source voltage V
dd
is 3V or more, it can be applied by lowering the threshold voltage (V
th
) of the transistor. However, in reality, V
dd
cannot be applied when the power source voltage V
dd
is lower than 2V.
Below, an explanation will be made more in detail on this matter.
First, the required limiting conditions to the circuit of
FIG. 13
include the following two items.
1: In order to raise the output voltage V
out
to a level of the high voltage V
pp
, the formula, V
th(NT11)
(V
bb
+V
pp
)+V
th(NT12)
(V
BB
=V
pp
)≦V
dd
, should be applied.
Accordingly, V
th
(V
BB
=V
pp
) has to be small to lower the voltage.
2: Before the clock signal CLK energizes the capacitor C
11
, it is necessary to convey the V
dd
level of the signal SIG
1
to the output terminal T
out
side and attain the level of at least V
out
≧V
th(NT11)
(V
BB
=0V)
When the above condition is not met, The NMOS transistor NT
11
is held cut off and the level converting operation do
Callahan Timothy P.
Englund Terry L.
Kananen Ronald P.
Rader Fishman & Grauer
Sony Corporation
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