Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
2000-07-14
2003-05-20
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S537000, C326S068000, C326S081000
Reexamination Certificate
active
06566930
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a level shift circuit usable in a semiconductor device which operates internally at a low voltage.
LSIs (Large-Scale Integrated circuits) have been advancing toward higher speeds and higher integrations with the progress of microfabrication techniques. Low power consumption of LSIs is one of key techniques for practical use of LSIs that operate at high speed. For high-speed operation of these LSIs, because larger power consumption is involved, ceramic packages are adopted for stable operation, or radiation fins and the like are necessitated, which poses a problem that the cost increases. Also, in the case of small-size, lightweight portable equipment which is popular these days, low power consumption is of importance from the point of view of running time of batteries as well.
Although lowering the operating voltage is very effective in lowering the power consumption of an LSI, there is a need of enlarging input/output signal swings in order that signal exchange with other LSIs is enabled even if internal operating voltage VDD is lowered, in which case a level shift circuit for enlarging signal swings is necessitated.
A conventional LSI that operate with low voltage is provided with a level shift circuit shown in
FIG. 10
, which interfaces externally with a voltage higher than the LSI's internal voltage. This level shift circuit, as shown in
FIG. 10
, has: an N-channel MOS (Metal Oxide Semiconductor) field effect transistor (hereinafter, referred to as NMOS transistor) N
101
to the gate of which an input signal A is supplied and the source of which is connected to the ground GND; a P-channel MOS field effect transistor (hereinafter, referred to as PMOS transistor) P
101
the drain of which is connected to the drain of the NMOS transistor N
101
and to the gate of which the input signal A is connected; an NMOS transistor N
102
to the gate of which the input signal A is connected and the source of which is connected to the ground GND; an NMOS transistor N
103
the gate of which is connected to the drain of the NMOS transistor N
101
and the source of which is connected to the ground GND; a PMOS transistor P
102
the gate of which is connected to the drain (node
102
) of the NMOS transistor N
103
and the drain of which is connected to the drain (node
101
) of the NMOS transistor N
102
and the source of which is connected to power supply VCC; and a PMOS transistor P
103
the gate of which is connected to the drain (node
101
) of the NMOS transistor N
102
and the source of which is connected to the power supply VCC and the drain of which is connected to the drain (node
102
) of the NMOS transistor N
103
. The NMOS transistor N
101
and the PMOS transistor P
101
constitute an inverter circuit IV
100
, and this inverter circuit IV
100
operates with internal power supply VDD (<VCC) connected to the source of the PMOS transistor P
101
and outputs an inverted signal of the input signal A. Then, the level shift circuit shifts the level of the input signal A to produce an output signal Y having a swing larger than that of the input signal A.
However, when a large level shift amount is involved, for example, when a swing of 0.5 V is changed to a swing of 3.3 V, because the driving current of the MOS transistor that operates at 0.5 V is small, the delay time of the circuit is increased, causing a problem of lowered operating speed of the circuit. As a solution to it, it is conceivable to lower the threshold, voltage Vth of the MOS transistor so that the driving current of the MOS transistor does not become so small even at low voltage. However, lowering the threshold voltage Vth would cause the leak current of the MOS transistor to increase, posing a problem that the power consumption increases due to the leak current even in the standby mode. Also, employing a microfabrication process in which the gate oxide is reduced in film thickness to increase the driving current of the MOS transistor that operates at 0.5 V would lead to a problem that the transistor would not be able to endure a voltage of 3.3. V, leading to breakdown.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a level shift circuit capable of realizing low power consumption without lowering the operating speed at a low voltage, while securely preventing the breakdown with ease.
In order to accomplish the above object, according to a first aspect of the present invention, there is provided a level shift circuit for providing an output signal having a swing larger than a swing of an input signal, the level shift circuit including a plurality of MOS transistors constituting a circuit operative at a low voltage and a circuit to which a voltage higher than the low voltage is applied, wherein among the plurality of MOS transistors, at least one of MOS transistors to gates of which a signal having a swing corresponding to the swing of the input signal is supplied is a MOS transistor whose channel forming semiconductor region is electrically connected to its gate.
Note here that the words “channel forming semiconductor region” of a MOS transistor refers to a semiconductor region where a channel is to be formed when the transistor is turned on.
Also, there is provided a level shift circuit, according to a second aspect of the present invention, for providing an output signal having a swing smaller than a swing of an input signal, the level shift circuit including a plurality of MOS transistors constituting a circuit operative at a low voltage, wherein at least one of the plurality of MOS transistors is a MOS transistor whose channel forming semiconductor region is electrically connected to its gate.
Also, there is provided a level shift circuit according to a third aspect of the invention, comprising:
an inverter circuit having a first first-conductivity-type MOS transistor and a first second-conductivity-type MOS transistor connected complementary to each other between a first power supply and a ground, the inverter circuit providing an inverted signal of an input signal;
a second first-conductivity-type MOS transistor to a gate of which the input signal is connected and a source of which is connected to the ground;
a third first-conductivity-type MOS transistor to a gate of which an output of the inverter circuit is connected, and a source of which is connected to the ground;
a second second-conductivity-type MOS transistor whose gate is connected to a drain of the third first-conductivity-type MOS transistor, and whose source is connected to a second power supply, and whose drain is connected to a drain of the second first-conductivity-type MOS transistor; and
a third second-conductivity-type MOS transistor whose gate is connected to the drain of the second first-conductivity-type MOS transistor, and whose source is connected to the second power supply, and whose drain is connected to the drain of the third first-conductivity-type MOS transistor, wherein
the first first-conductivity-type MOS transistor and the first second-conductivity-type MOS transistor of the inverter circuit, and the second and third first-conductivity-type MOS transistors are each a MOS transistor whose channel forming semiconductor region is electrically connected to its gate.
Furthermore, a level shift circuit of a fourth aspect of the invention comprises an inverter circuit having a first-conductivity-type MOS transistor and a second-conductivity-type MOS transistor connected complementary to each other between a power supply and a ground, the inverter circuit providing an inverted signal of an input signal, the inverted signal shifted in level to a swing smaller than a swing of the input signal, wherein either one of the first-conductivity-type MOS transistor or the second-conductivity-type MOS transistor of the inverter circuit is a MOS transistor whose channel forming semiconductor region is electrically connected to its gate.
Still further, there is provided a level shift circuit according to a fifth aspect of the invention comprising:
Cunningham Terry D.
Nguyen Long
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