Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
1998-09-15
2001-06-05
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C326S062000, C326S081000
Reexamination Certificate
active
06242962
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a level shift circuit and, more particularly, to a level shift circuit for stepwise changing a potential range without applying large potential difference to component field effect transistors.
DESCRIPTION OF THE RELATED ART
A flash write memory device is a kind of electrically erasable and programmable read only memory device, and requires not only a signal changed between a positive power voltage level Vcc and a ground level GND but also a signal changed between the ground level GND and a negative erase voltage −Vpp. The negative erase voltage −Vpp is lower than the ground voltage GND by value Vpp, and the value Vpp is greater than value Vcc. The positive power voltage Vcc is usually 5 volts, and the negative erase voltage −Vpp is −12 volts. For this reason, the flash write memory device requires a level shift circuit, which shifts the signal changed between the positive power voltage Vcc and the ground level GND to the signal changed between the ground level GND and the negative erase voltage −Vpp.
FIG. 1
illustrates a typical example of the level shift circuit. The prior art level shift circuit comprises a first-stage level shifter
1
and a second stage level shifter
2
. The first stage level shifter
1
changes a signal from the potential range between the positive power voltage Vcc and the ground level GND to a potential range between the positive power voltage Vcc and the negative voltage −Vpp, and the second stage level shifter
2
changes the signal from the potential range between the positive power voltage Vcc and the negative voltage −Vpp to another potential range between the ground level GND and the negative voltage −Vpp.
The first-stage level shifter
1
includes an inverter
1
a
connected to an input node N
1
, a series combination of a p-channel enhancement type field effect transistor
1
b
and an n-channel enhancement type field effect transistor
1
c
and another series combination of a p-channel enhancement type field effect transistor
1
d
and an n-channel enhancement type field effect transistor
1
e
arranged in parallel to the series combination. The series combination of the p-channel enhancement type field effect transistor
1
b
and the n-channel enhancement type field effect transistor
1
c
is connected between the positive power supply line VCC and the negative voltage line −VPP, and the input node N
1
and the output node of the inverter
1
a
are connected to the gate electrode of the p-channel enhancement type field effect transistor
1
b
and the gate electrode of the other p-channel enhancement type field effect transistor
1
d
, respectively. The common drain nodes N
2
/N
3
are connected to the gate electrode of the n-channel enhancement type field effect transistor
1
e
and the gate electrode of the n-channel enhancement type field effect transistor
1
c
, respectively. The common drain node N
3
serves as an output node of the first-stage level shifter
1
.
The first-stage level shifter
1
behaves as follows. An input signal S
1
is changed between the positive power voltage level Vcc and the ground level GND. Assuming now that the input signal S
1
is changed from the ground level GND to the positive power voltage Vcc, the inverter
1
a
inverts the potential level of the input signal S
1
so as to produce the complementary input signal CS
1
of the ground level GND. The input signal S
1
and the complementary input signal CS
1
are supplied to the gate electrode of the p-channel enhancement type field effect transistor
1
b
and the gate electrode of the p-channel enhancement type field effect transistor
1
d
. The input signal S
1
causes the p-channel enhancement type field effect transistor
1
b
to turn off, and the complementary input signal CS
1
causes the other p-channel enhancement type field effect transistor
1
d
to turn on. The common drain node N
2
is isolated from the positive power voltage line VCC, and the other common drain node N
3
is electrically connected to the positive power supply line VCC. Then, the positive power voltage Vcc at the common drain node N
3
causes the n-channel enhancement type field effect transistor
1
c
to turn on, and the negative voltage −VPP is supplied to the other common drain node N
2
. The negative voltage −VPP at the common drain node N
2
causes the other n-channel enhancement type field effect transistor
1
e
to turn off. Thus, the first-stage level shifter
1
changes the potential level at the common drain node N
3
to the positive power voltage level Vcc, and supplies an intermediate signal S
2
of the positive power voltage level Vcc to the second-stage level shifter
2
.
On the other hand, when the input signal S
1
is changed to the ground level GND, the inverter
1
a
changes the complementary input signal CS
1
to the positive power voltage Vcc, and the input signal S
1
and the complementary input signal CS
1
are supplied to the gate electrode of the p-channel enhancement type field effect transistor
1
b
and the gate electrode of the p-channel enhancement type field effect transistor
1
d
, respectively. The p-channel enhancement type field effect transistor
1
d
turns off, and the other p-channel enhancement type field effect transistor
1
b
turns on. The positive power voltage Vcc is supplied to the common drain node N
2
, and the other common drain node N
3
is isolated from the positive power supply line VCC. The positive power voltage Vcc at the common drain node N
2
causes the n-channel enhancement type field effect transistor
1
e
to turn on, and the negative voltage −Vpp is supplied to the common drain node N
3
. The negative voltage −Vpp causes the other n-channel enhancement type field effect transistor
1
c
to turn off, and the intermediate signal S
2
is fixed to the negative voltage −Vpp. Thus, the intermediate signal S
2
is changed between the positive power voltage Vcc and the negative voltage −Vpp.
The second-stage level shifter
2
includes a series combination of p-channel enhancement type field effect transistor
2
a
and an n-channel enhancement type field effect transistor
2
b
connected between the ground line GND and the negative voltage line −VPP. The intermediate signal S
2
is supplied to the gate electrode of the p-channel enhancement type field effect transistor
2
a
and the gate electrode of the n-channel enhancement type field effect transistor
2
b
, and an output signal S
3
is supplied from the common drain node N
4
to an output node N
5
.
When the intermediate signal S
2
is in the positive power voltage Vcc, the n-channel enhancement type field effect transistor
2
b
turns on, and the p-channel enhancement type field effect transistor
2
a
turns off. As a result, the output signal S
3
is changed to the negative voltage −Vpp. On the other hand, if the intermediate signal S
2
is changed to the negative voltage −Vpp, the n-channel enhancement type field effect transistor
2
b
turns off, and the p-channel enhancement type field effect transistor
2
a
turns on. Then, the output signal S
3
is changed to the ground level GND. Thus, the potential range between the positive power voltage Vcc and the ground level GND is changed through the potential range between the positive power voltage Vcc and the negative voltage −Vpp to the potential range between the ground level GND and the negative voltage −Vpp.
The manufacturer has increased the memory capacity of the flash write memory device, and still makes research and development efforts on increase of the memory capacity. The component field effect transistors are scaled down, and the p-channel enhancement type field effect transistors
1
b
/
1
d
/
2
a
and the n-channel enhancement type field effect transistors
1
c
/
1
d
/
2
b
are miniaturized. The component field effect transistors
1
b
/
1
d
/
2
a
and
1
c
/
1
d
/
2
b
are further scaled down, and the gate insulating layers are getting thinner and t
Callahan Timothy P.
Luu An T.
McGinn & Gibb PLLC
NEC Corporation
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