Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
2002-09-17
2004-04-06
Nguyen, Minh (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C326S063000, C326S080000
Reexamination Certificate
active
06717453
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to a level shift circuit and more particularly to a level shift circuit that may provide an interface between internal circuits of a semiconductor integrated circuit and external circuits and/or between internal circuits of a semiconductor integrated circuit operating from different power supply potentials.
BACKGROUND OF THE INVENTION
A level shift circuit can be used as an interface between circuits operating at different power supply voltages. A level shifter can receive a signal having a first power supply level and provides a signal having a second power supply level. As manufacturing processes become finer and/or lower power consumption becomes desirable, internal circuits of a semiconductor integrated circuit (such as a large scale integrated circuit—LSI) are reduced. However, a semiconductor integrated circuit can be included in a system operating at a higher power supply voltage. In this case, an interface circuit is required to provide an interface between external signals and internal signals having different voltage swings. In systems in which the system voltage has not been stepped down, the difference between the system power supply potential and the power supply potential for internal circuits on a semiconductor integrated circuit can be great. Because different systems may operate at different power supply potentials, the interface circuit needs to operate over a wide range. However, sizing of devices in a level shift circuit may be different for optimal performance at different power supply potentials. Due to the need to provide an interface circuit that operates over such a wide range of power supply potentials, design and development time may be increased.
Also, in order to provide a LSI that can have low power consumption capabilities and/or high speed capabilities as required by the system, a method has been established in which an LSI is operated by changing internal and/or external poser supply voltages during usage as necessary. This has led to a demand that a wide range of internal and external voltages being supported with a single level shift circuit while maintaining operating characteristics (such as delay time). Additionally, in recent years, a complementary signal output has been adopted or a method with which data is sampled/provided by detecting a rising and a falling edge of a clock signal. As a result, in a level shift circuit, it has become increasingly important that differences in delay times occurring when an output signal rises and a delay time when an output signal falls be reduced or eliminated.
Referring to
FIG. 9
, a circuit schematic diagram of a conventional level shift circuit is set forth and given the general reference character
101
.
Conventional level shift circuit
101
includes inverters (
111
and
112
) and a level shift flip-flop portion
113
. Level shift circuit
101
is supplied with power supply voltages (VDD
1
and VDD
2
), where power supply voltage VDD
1
≦power supply voltage VDD
2
. Inverter
111
is constructed from n-channel transistor N
101
and p-channel transistor P
101
. Inverter
112
is constructed from n-channel transistor N
102
and p-channel transistor P
102
. Level shifter flip-flop portion
113
is constructed from n-channel transistors (N
103
and N
104
) and p-channel transistors (P
103
and P
104
).
In level shift circuit
101
, the drive capabilities of p-channel transistors (P
103
and P
104
) are set to be small and the drive capabilities of n-channel transistors (N
103
and N
104
) are set to be large in order to support a wide range of differences between internal and external voltages. In order to support such a wide range of differences, a large difference between driving capabilities are maintained in this manner. However, because of the drive capability differences, a large difference between an input-output delay time (delay time between an input signal at terminal A and an output signal at terminal Y) occurs between an input-output delay time for a rising edge signal and a falling edge signal.
In order to reduce such a difference between input-output delay times, JP 2001-068991 A and JP 11-239051 A disclose level shift circuits where an output terminal of the level shift circuit is provided with a pull-up circuit.
Referring now to
FIG. 10
, a circuit schematic diagram of a conventional level shift circuit as disclosed in JP 2001-068991 A is set forth. The conventional level shift circuit of
FIG. 10
includes a level shift portion
101
(identical to level shift circuit
101
of
FIG. 9
) and a pull-up portion
102
. Pull-up portion
102
includes p-channel transistors (P
121
and P
122
) and inverters (
121
and
122
).
Referring now to
FIG. 11
, a circuit schematic diagram of a conventional level shift circuit as disclosed in JP 2001-239051 A is set forth. The conventional level shift circuit of
FIG. 11
includes a level shift portion
101
(identical to level shift circuit
101
of
FIG. 9
) and a pull-up portion
102
a
. Pull-up portion
102
a
includes p-channel transistors (P
123
and P
124
) and inverters (
123
and
124
).
In conventional level shift circuits illustrated in
FIGS. 10 and 11
, by providing pull-up portions (
102
and
102
a
), it may be possible to improve an input-output delay time in the case of a rising output signal.
However, the conventional level shift circuit disclosed in JP 2001-068991 A (
FIG. 10
) has a drawback in that if a potential difference between power supply voltage VDD
1
and power supply voltage VDD
2
is increased, the effect of pull-up portion
102
is reduced and the difference between input-output delay times are increased. Also, the conventional level shift circuit disclosed in JP 11-239051 A (
FIG. 11
) has a drawback that if the power supply voltage VDD
2
fluctuates, the pull-up capabilities of pull-up portion
102
a
also varies which causes the difference between input-output delay times to vary.
Also, in conventional level shift portion
101
, the delay time difference tends to vary in accordance with the fluctuations of power supply voltages. When power supply voltage VDD
1
fluctuates the gate to source voltage (Vgs) of n-channel transistors (N
103
and N
104
) vary and the drive capabilities of n-channel transistors (N
103
and N
104
) vary accordingly. Consequently, a delay time occurring when the potential of a terminal (
114
or
115
) switches from a logic high level to a logic low level varies. On the other hand, when power supply voltage VDD
2
fluctuates, the gate to source voltages (Vgs) of p-channel transistors (P
103
and P
104
) vary and the drive capabilities of p-channel transistors (P
103
and P
104
) vary accordingly. Consequently, a delay time occurring when the potential of terminal (
114
or
115
) switches from a logic low level to a logic high level varies.
For the reasons described above, an input-output delay time for both a rising output signal and a falling output signal can vary in accordance with variations in power supply voltages (VDD
1
and VDD
2
). Also, the difference between the delay times between a rising output signal and a falling output signal varies in accordance with variations in power supply voltages (VDD
1
and VDD
2
). As a result, conventional level shift circuits have a drawback in that when an internal power supply voltage or an external power supply voltage fluctuates, it may be difficult to reduce a difference between an input-output delay time between a rising output signal and a falling output signal.
In view of the above discussion, it would be desirable to provide level shift circuit that may be capable of improving delay time characteristics and reducing a difference between delay times even if a power supply voltage fluctuates over a wide range.
SUMMARY OF THE INVENTION
According to the present embodiments, a level shift circuit that may have reduced input-output timing differences is disclosed. A level shift circuit may include a level shift portion and a signal selection portion. A level shift portion may receive
NEC Electronics Corporation
Nguyen Minh
Sako Bradley T.
Walker Darryl G.
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