Level shift circuit for interfacing between two different voltag

Details Level shift circuit for interfacing between two different voltag Level shift circuit for interfacing between two different voltag

1984-08-21

1987-08-04

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307455, 307356, 307358, 330257, 323316, H03K 19092, H03K 19086, H03K 19003, H03K 1710

Patent

active

046848312

ABSTRACT:
A novel translator for translating linear logic signal levels to TTL-compatible levels in an integrated logic device having an I/O section including a mix of ECL and TTL circuit. The translator includes a resistive circuit connected to a current mirror and a linear buffer circuit connected between the resistive circuit and current mirror. The linear buffer responds to a linear logic signal by switching a current into and out of a portion of the resistive circuit which is added to or subtracted from the current mirror current flowing through the resistive network. The resulting variable current causes the resistive network to produce a TTL-compatible control voltage signal which drives a TTL buffer, causing it to produce standard TTL signals in response to linear logic signals applied to the linear buffer.

REFERENCES:
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patent: 4456838 (1984-06-01), Taguchi et al.
patent: 4485318 (1984-11-01), Sano
patent: 4490630 (1984-12-01), Freeman
patent: 4527079 (1985-07-01), Thompson
patent: 4536664 (1985-08-01), Martin
patent: 4578602 (1986-03-01), West et al.
AMCC Device Specification--"Q700 Series Logic Arrays", pp. 1-7.
"Speed/Power-Programmable Arrays Slash System Power Consumption", by Mark P. Huang, Richard W. Spehn & Ray C. Yuen, EDN, May 3, 1984.
AMCC Brochure--"Converting Your Designs into High Performance ECL/TTL Logic Arrays".

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