Level shift circuit for converting a signal in an ecl level into

Details Level shift circuit for converting a signal in an ecl level into Level shift circuit for converting a signal in an ecl level into

1988-11-25

1990-03-06

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307446, 307570, 307443, 307448, 307542, 307547, 307548, H03K 19092, H03K 19003, H03K 19086, H03K 1710

Patent

active

049068717

ABSTRACT:
A level shift circuit is made up of a capacitor, a MOS inverter, and a bias circuit for applying a bias voltage to an input node of the MOS inverter. A first electrode of the capacitor is connected to an output stage of an ECL circuit, while a second electrode to the input node of the MOS inverter. The output node of the MOS inverter is coupled with an input stage of a CMOS circuit. An output signal of the ECL circuit is capacitively coupled with the input node of the MOS inverter so that it is superposed onto a bias voltage being supplied from the bias circuit. A level of this signal is shifted to a CMOS logic level by the MOS inverter, and then applied to the input stage of the CMOS circuit.

REFERENCES:
patent: 4029971 (1977-06-01), Pryor
patent: 4316105 (1982-02-01), Fowler
patent: 4518880 (1985-05-01), Masuda et al.
patent: 4697109 (1987-09-01), Honma et al.
patent: 4703198 (1987-10-01), Porter et al.
patent: 4754165 (1988-06-01), Cornish
patent: 4797583 (1989-01-01), Ueno et al.
Oqiue et al., "13-ns, 500-mW, 64-kbit ECL RAM Using, HI-BICMOS Technology," IEEE Journal of Solid-State Circuits, vol. SC-21, No. 5, Oct. 1986, pp. 681-685.

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