Computer graphics processing and selective visual display system – Display driving control circuitry
Reexamination Certificate
2000-07-14
2003-02-18
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
C345S211000, C345S214000, C326S062000, C326S081000, C327S333000
Reexamination Certificate
active
06522323
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a level shift circuit and an image display device employing the circuit, and in particular, to a level shift circuit that is incorporated in an image display device of a driver monolithic type (drive circuit integrated type) and amplifies an input signal having small amplitude (logic level) and the image display device.
In recent years, researches and developments of display devices employing liquid crystals have been remarkably promoted, and in particular, a TFT (Thin Film Transistor) liquid crystal display device employing polysilicon is expected to have great demands in future. The TFT liquid crystal display device employing polysilicon has electron and hole mobility that is two orders of magnitude greater than that of a device employing amorphous silicon and is able to have a CMOS structure of a combination of an n-channel TFT and a p-channel TFT. Therefore, in contrast to the TFT liquid crystal display device employing amorphous silicon in which the drive circuit must be formed of, for example, single crystal silicon outside the substrate of a pixel TFT for a liquid crystal cell, a drive circuit can be formed on a substrate identical to that of the pixel TFT for the liquid crystal cell using polysilicon. That is, a driver monolithic type TFT liquid crystal display device can be formed, and this allows the compacting, functional improvement and cost reduction to be achieved.
FIG. 11
shows the construction of the driver monolithic type TFT liquid crystal display device.
FIG. 11
shows a video signal terminal
1
for inputting a video signal from the outside, a counter voltage terminal
2
for inputting a voltage to an opposite electrode, a shift register
3
for driving n (n: integer n>1) gate bus lines, a shift register
4
for driving m (m: integer m>1) source bus lines, level shift circuits
5
through
8
for amplifying the amplitude of an input control signal, a start pulse SPV to be inputted to the shift register
3
, clock signals &phgr;
1
V and &phgr;
2
V having a frequency equal to a horizontal period, drive pulses &phgr;V
1
through &phgr;Vn that are to turn on and off TFT elements and outputted from the shift register
3
, gate bus lines G
1
through Gn, a start pulse SPH to be inputted to the shift register
4
, clock signals &phgr;
1
H and &phgr;
2
H having a frequency m times the horizontal period, sampling pulses &phgr;H
1
through &phgr;Hm outputted from the shift register
4
, sampling switches M
1
through Mm to sample a video signal, source bus lines L
1
through Lm, TFT elements M
11
through Mnm provided at the intersections of the source bus lines L
1
through Lm and the gate bus lines G
1
through Gn and liquid crystal cells C
11
through Cnm that exist between the pixel electrodes and the opposite electrodes connected to the TFT elements M
11
through Mnm.
In
FIG. 11
, the level shift circuits
5
through
8
are provided with a circuit for amplifying the amplitudes of the start pulses SPV and SPH and the clock signals &phgr;
1
V, &phgr;
2
V, &phgr;
1
H and &phgr;
2
H. In the driver monolithic type TFT liquid crystal display device, the drive circuit is constructed of polysilicon. However, the threshold voltage of the transistor becomes higher than that of a device whose drive circuit is formed of single crystal silicon. Therefore, the amplification levels of the start pulses SPV and SPH and the clock signals &phgr;
1
V, &phgr;
2
V, &phgr;
1
H and &phgr;
2
H, which have logic level power voltages of 3 V, 3.3 V and 5 V, are not regarded as sufficiently high. The levels are required to be raised up to a voltage of, for example, 12 to 15 V, for which the level shift circuits
5
through
8
are provided.
FIG. 12
shows a conventional level shift circuit.
FIG. 12
shows a positive power voltage V
DD
, a negative power voltage GND, an input signal IN, an input signal (/IN) whose voltage level is inverted relative to the input signal IN, an output signal OUT, p-channel TFT's p
121
, p
122
and p
123
, and n-channel TFT's n
121
, n
122
and n
123
.
In
FIG. 12
, the input signal IN is inputted to the gate of an n-channel TFT n
121
, while the input signal (/IN) is inputted to the gate of an n-channel TFT n
122
. The drain of the n-channel TFT n
121
is connected to the drain and gate of a p-channel TFT p
121
and the gate of a p-channel TFT p
122
, while the drain of the n-channel TFT n
122
is connected to the drain of the p-channel TFT p
122
and an input terminal of an inverter circuit section constructed of a p-channel TFT p
123
and an n-channel TFT n
123
. The source of the p-channel TFT p
121
and the source of the p-channel TFT p
122
are connected to the positive power voltage V
DD
, while the source of the n-channel TFT n
121
and the source of the n-channel TFT n
122
are connected to the negative power voltage GND.
Reference is made to the operation of the conventional level shift circuit shown in FIG.
12
. If the input signal IN has high level and the input signal (IN) has low level, then the n-channel TFT n
121
is turned on, and the n-channel TFT n
122
is turned off. Then, the negative power voltage GND is inputted to the gate of the p-channel TFT p
121
and the gate of the p-channel TFT p
122
, when the p-channel TFT p
121
is regarded as a resistance component, flowing a current between the positive power voltage V
DD
and the negative power voltage GND. On the other hand, the p-channel TFT p
122
is turned on, by which the drain of the p-channel TFT p
122
and the input terminal of the inverter circuit section constructed of the p-channel TFT p
123
and the n-channel TFT n
123
are charged with the positive power voltage V
DD
, outputting the negative power voltage GND from the output terminal of the inverter circuit section. If the input signal IN is inverted to low level and the input signal (/IN) is inverted to high level, then the n-channel TFT n
121
is turned off, and the n-channel TFT n
122
is turned on. Then, the input terminal of the inverter circuit section constructed of the p-channel TFT p
123
and the n-channel TFT n
123
is discharged to the negative power voltage GND, and the positive power voltage V
DD
is outputted from the output terminal of the inverter circuit section. That is, the amplitude of the input is signal IN is amplified by the conventional level shift circuit shown in FIG.
12
. (It is to be noted that a potential difference between the positive power voltage V
DD
and the negative power voltage GND is set higher than the amplitude of the input signal IN).
If the conventional level shift circuit shown in
FIG. 12
is constructed of polysilicon similarly to the other drive circuit, then the threshold voltage of each transistor becomes higher than the voltage formed by single crystal silicon. During the processes of forming transistors, it is sometimes the case where variation in threshold voltage increases. The rise in transistor threshold voltage leads to an increase in transistor ON-state resistance. If the ON-state resistances of the p-channel TFT's p
121
and p
122
and the n-channel TFT's n
121
and n
122
become high, then a time constant of charging and discharging the input terminal of the inverter circuit section constructed of the p-channel TFT p
123
and the n-channel TFT n
123
is increased. In contrast to this, the amplitudes of the start pulses SPV and SPH and the clock signals &phgr;
1
V, &phgr;
2
V, &phgr;
1
H and &phgr;
2
H, which have logic level power voltages of 3 V, 3.3 V and 5 V, are not regarded as sufficiently high. This has led to the problem that the waveform of an output from the level shift circuit has become dull or distorted.
In view of the above, it can be considered to increase the transistor channel width in order to reduce the time constant. However, if the transistor channel width is increased, then this leads to the increase in area of the level shift circuit. Furthermore, if the transistor channel width is increased, then the capacity of the transistor itself concurrently increases
Ogawa Yasuyuki
Sasaki Osamu
Takafuji Yutaka
Lewis David L
Nixon & Vanderhye P.C.
Sharp Kabushiki Kaisha
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