Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
2000-12-15
2002-03-19
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S535000, C327S589000, C326S080000
Reexamination Certificate
active
06359493
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an improvement in level shift circuits for level shifting a low voltage signal to a high voltage signal to perform a signal transfer between two different circuits which are operated by different power supply voltages.
Recent increasing demand for low-power electronic devices has caused the power supply voltage of LSI internal circuits to decrease to 3 volts, to 2.5 volts or to less than 2.5 volts. This produces some necessities. For example, if an LSI external circuit is operated by 5 volts in contrast with the fact that the power supply voltage of a corresponding LSI internal circuit is 3 volts or less, this results in the requirement that an amplitude of 5 volts be provided. To this end, it is required to provide a level shift circuit capable of shifting either an amplitude of 3 volts, an amplitude of 2.5 volts or an amplitude of less than 2.5 volts to an amplitude of 5 volts.
Referring first to
FIG. 10
, there is shown an example of a conventional level shift circuit. Reference numeral
301
designates a signal input terminal. The signal input terminal
301
receives a low voltage (3 volts) signal from an inverter (an external circuit)
20
which is operated by low oltages (e.g., 3 volts).
302
designates an output signal terminal at which a high voltage (5 volts) signal is output to an operating circuit (not shown in the figure) which is operated by higher voltages (e.g., 5 volts).
Referring still to
FIG. 10
,
401
designates a first power supply terminal which is coupled to a low voltage power supply (e.g., a 3-V power supply).
402
designates a second power supply terminal which is coupled to a high voltage power supply (e.g., a 5-V power supply).
304
designates an N-channel MOS (Nch) transistor having (i) terminals of which one is coupled to the signal input terminal
301
and (ii) a gate which is coupled to the first power supply terminal
401
.
303
designates an inverter made up of an Nch transistor
306
and a P-channel MOS (Pch) transistor
307
. The inverter
303
receives its operating voltage from the second power supply terminal
402
. The inverter
303
has an input coupled to the other of the terminals of the Nch transistor
304
. Further, the inverter
303
has an output coupled to the output signal terminal
302
.
305
designates a Pch transistor having terminals, namely a drain, a source, and a gate, wherein the drain terminal is coupled to the input of the inverter
303
, the source terminal is coupled to the second power supply terminal
402
, and the gate terminal is coupled to the output of the inverter
303
.
403
designates an intermediate node between the Nch transistor
304
and the inverter
303
.
Referring to FIG.
11
(
a
), the operation of the level shift circuit of
FIG. 10
will be described below.
Upon application of a signal which changes in voltage level from LOW (0 volt) to HIGH (3 volts) at the signal input terminal
301
, the intermediate node
403
is pulled up to a voltage level (3−Vtn) through the Nch transistor
304
in the ON state, where Vtn represents the threshold voltage of the Nch transistor
304
. If the switching voltage of the inverter
303
, Vo. is set lower than the voltage (3−Vtn), this causes the output signal terminal
302
to decrease from HIGH (5 volts) towards LOW (0 volt) by signal inversion.
Because of a gate potential drop, the Pch transistor
305
goes into the ON state from the OFF state, and the intermediate node
403
is pulled up to HIGH (5 volts). Accordingly, the potential of the output signal terminal
302
is decreased to a lower value, finally arriving at LOW (0 volt). The Nch, transistor
304
comes to have a gate potential equal to or less than its source and drain potentials, as a result of which the Nch transistor
304
changes to the OFF state. Accordingly, there exists no current path extending from the high voltage power supply to the low voltage power supply, which makes it possible to perform a voltage level shifting operation in the steady state with direct currents cut off.
Next, upon application of a signal which changes in voltage level from HIGH (3 volts) to LOW (0 volt) at the signal input terminal
301
, the gate potential of the Nch transistor
304
will relatively increase. The Nch transistor
304
, therefore, changes to the ON state. The intermediate node
403
is decreased from HIGH (5 volts) towards LOW (0 volt). The Pch transistor
305
is in the ON state and the potential level of the intermediate node
403
is determined by the value of a sum of the ON resistance of the Nch transistor
304
and the ON resistance of the external circuit
20
which drives the signal input terminal
301
with respect to the ON resistance of the Pch transistor
305
. That is, as the ON resistance of the Pch transistor
305
relatively increases, the potential level of the intermediate node
403
decreases. Accordingly, if the Pch transistor's ON resistance is set sufficiently greater than the aforesaid sum, this causes the intermediate node
403
to have a potential level below Vo (the inverter's
303
switching voltage) and signal conversion causes the output signal terminal
302
to increase from LOW (0 volt) towards HIGH (5 volts).
Because of such an operation, the Pch transistor
305
continues to be boosted in gate potential, and the ON resistance further increases. As a result, the potential of the intermediate node
403
is decreased to a lower value and the voltage of the output signal terminal increases. Finally, the Pch transistor
305
enters the OFF state and the intermediate node
403
arrives at LOW (0 volt) while the output signal terminal arrives at HIGH (5 volts). Also in this case, there exists no current path extending from the high voltage power supply to the low voltage power supply, which makes it possible to perform a voltage level shifting in the steady state with direct currents cut off.
Because of the foregoing operations, a signal of opposite phase to the input signal at the signal input terminal
301
appears at the output signal terminal
302
. Such an inverted signal has an amplitude of 5 volts.
However, the above-described conventional level shift circuit has some drawbacks. One drawback is that both the possibility that the operating speed degrades and the possibility that the malfunction occurs increase when the low voltage power supply is decreased in voltage level to a further extent because of demands for lower power LSI circuits.
In the case the, signal input terminal
301
makes a change in voltage level from LOW to HIGH, a voltage level drop occurring in the low voltage power supply results in a speed drop which pulls up the potential of the intermediate node
403
, for the drain current is reduced because both the drive performance of the external circuit
20
for driving the signal input terminal
301
and the gate voltage of the Nch transistor
304
in the ON state fall.
The reachable potential of the intermediate node
403
will fall for an amount approximately corresponding to a voltage level drop in the low voltage power supply. If such a reachable potential does not exceed Vo (the switching voltage of the inverter
303
), no signal inversion is carried out, which causes the output signal terminal
302
to remain at HIGH. As a result, a malfunction occurs. Such a malfunction may be avoided by reducing the switching voltage. To this end, the gate width of the Nch transistor
306
forming a part of the inverter is required to be set relatively greater than that of the Pch transistor
307
. However, the Pch transistor
307
is, of course, required to maintain some drive performance (gate width) and a reduction of the switching potential results in an abrupt increase in LSI pattern area. Therefore, such arrangement cannot be employed.
In addition to the above, if the gate width of the Nch transistor
306
is increased, this results in a gate capacitance load increase. This is a factor of degrading the operating speed.
A drop in the voltage level of the low voltage po
Callahan Timothy P.
Harness & Dickey & Pierce P.L.C.
Luu An T.
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