Level sensitive reset circuit for digital logic

Details Level sensitive reset circuit for digital logic Level sensitive reset circuit for digital logic

1982-06-17

1984-03-20

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307593, 307603, 307470, 307311, 328 73, H03K 1728

Patent

active

044383576

ABSTRACT:
A circuit is provided for resetting a digital logic circuit, such as a digital counter. A switch 16 provides a first signal when a predetermined condition has occcurred. A flip-flop 24 provides an output reset signal when the flip-flop is in a first state, in response to the first signal. The digital logic circuit to be reset 32 is coupled to the output of the flip-flop 24 for receiving its output reset signal. Feedback means 34, 36, 38 are coupled from the digital logic circuit 32 back to the flip-flop 24 for providing a signal to put the flip-flop into its other state whereby its output reset signal is terminated.

REFERENCES:
patent: 3510689 (1970-05-01), Baker
patent: 3576496 (1971-04-01), Garagnon
patent: 3618052 (1971-11-01), Kwei
patent: 3619665 (1971-11-01), Kosonocky
patent: 3742257 (1973-06-01), Wittenzellner
patent: 3867580 (1975-02-01), Russell
patent: 4085373 (1978-04-01), McConnell

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