Level sensitive reset circuit for digital logic

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

307593, 307603, 307470, 307311, 328 73, H03K 1728

Patent

active

044383576

ABSTRACT:
A circuit is provided for resetting a digital logic circuit, such as a digital counter. A switch 16 provides a first signal when a predetermined condition has occcurred. A flip-flop 24 provides an output reset signal when the flip-flop is in a first state, in response to the first signal. The digital logic circuit to be reset 32 is coupled to the output of the flip-flop 24 for receiving its output reset signal. Feedback means 34, 36, 38 are coupled from the digital logic circuit 32 back to the flip-flop 24 for providing a signal to put the flip-flop into its other state whereby its output reset signal is terminated.

REFERENCES:
patent: 3510689 (1970-05-01), Baker
patent: 3576496 (1971-04-01), Garagnon
patent: 3618052 (1971-11-01), Kwei
patent: 3619665 (1971-11-01), Kosonocky
patent: 3742257 (1973-06-01), Wittenzellner
patent: 3867580 (1975-02-01), Russell
patent: 4085373 (1978-04-01), McConnell

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Level sensitive reset circuit for digital logic does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Level sensitive reset circuit for digital logic, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Level sensitive reset circuit for digital logic will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1606516

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.