Level detector circuit, interface and method for interpreting an

Details Level detector circuit, interface and method for interpreting an Level detector circuit, interface and method for interpreting an

1997-06-12

1999-02-16

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

327 60, 327 68, 327333, 327336, H03K 5153

Patent

active

058724680

ABSTRACT:
To decode an attenuated multi-level signal (42) in a receive interface (120) of communication apparatus, first (134) and second (150) diode pumps co-operate with a biasing chain to ensure that threshold reference levels used by respective positive (52) and negative (54) data comparators are dynamically adjusted to a level dependent upon the attenuated multi-level signal (42) applied to the diode pumps. Particularly, a voltage divider (138-144) acts dynamically to bias differential inputs to the respective positive (52) and negative (54) data comparators, with a ratio between a biasing chain of resistors (138-144) and a common input resistor 128 determining the threshold reference levels used to assign logical levels for the reconstruction of symbols encoded within the multi-level signal (42).

REFERENCES:
patent: 5120995 (1992-06-01), Abdi
G703 Interface Port Specification.
Exar, XR-T5640 LSI design specification for PCM AMI Line Receiver and Clock Recovery Circuit.

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