Level detection circuit and ACC circuit employing the level dete

Details Level detection circuit and ACC circuit employing the level dete Level detection circuit and ACC circuit employing the level dete

1993-05-21

1995-02-21

Kostak, Victor R.

Television

Image signal processing circuitry specific to television

Chrominance signal amplitude control

348645, 348506, H04N 964

Patent

active

053920740

ABSTRACT:
A level detection circuit includes a multiplier and an adder for computing the sums of square values of a burst signal. A maximum value holding circuit holds a maximum value of the sums of the squared values of the burst signal. A counter counts sampling clocks. A multiplier, an adder and a 1/2 processing circuit compute a half value of the sum of two consecutive count values, and a delay circuit, a latch circuit and a comparator generate a first one of the two consecutive count values as a level of the burst signal when an output of the 1/2 processing circuit becomes larger than the output of the maximum value holding circuit. The invention enables level detection by finding a square value using a small circuit.

REFERENCES:
patent: 4092667 (1978-05-01), Akazawa et al.
patent: 4398209 (1983-08-01), Robitzsch
patent: 4523223 (1985-06-01), Luder et al.
patent: 4679072 (1987-07-01), Takayama

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