Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
2001-12-20
2003-05-13
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S218000, C327S333000
Reexamination Certificate
active
06563357
ABSTRACT:
FIELD
The present invention relates generally to latches, and more specifically to level converting latches in dual-supply voltage designs.
BACKGROUND
Latch circuits are widely used to temporarily store data and transfer the data from one part of a circuit to another part of the circuit. Integrated circuits such as microprocessors and memory devices often include a number of latch circuits and typically have a single supply voltage. However, because of demand for longer battery life in ultra low-power microprocessors and other circuits, designers have proposed a concept of dual-supply voltages. This concept allows critical units of the integrated circuits to operate at a higher supply voltage (Vcch) while non-critical units operate at a lower supply voltage (Vccl). When circuits operate at a lower voltage (Vccl), they operate slower but consume less power.
A problem arises when a unit operating at Vccl interfaces with a unit operating at Vcch. To solve this problem, level converting latches have been suggested.
FIG. 1
shows a prior art level converting latch
100
. Latch
100
receives a low swing signal or “Vccl signal,” Din, and outputs a high swing signal or “Vcch signal,” Dout. A Vccl signal has high potential level corresponding to Vccl; a Vcch signal has a high potential level corresponding to Vcch, which is greater than Vccl. Both Vccl and Vcch have the same low potential level, e.g., zero or ground. Latch
100
includes internal nodes A and B. Transistors N
1
and N
2
connect to nodes A and B and to transistor N
3
and inverter I
1
to allow node A or B to discharge to ground, in response to a potential level of a clock signal CLK. Cross-coupled inverters I
2
and I
3
connect to node A and B to operate as a conversion and a feedback circuit.
When the CLK signal switches from zero to Vcch, transistor N
3
turns on. Depending on the level of the Din signal, either node A or B selectively discharges to ground through transistors N
1
and N
3
or N
2
and N
3
. Inverters I
2
and I
3
convert the Vccl Din signal to a Vcch signal and hold it as potential levels at nodes A and B. Inverter I
4
drives the Vcch signal to an output of the latch as the Dout signal. As long as the CLK signal is at Vcch, latch
100
is transparent and the Vccl Din signal is available at an output of latch
100
as the Vcch Dout signal.
When the CLK signal switches from Vcch to zero, transistor N
3
turns off, stopping the effect of the Din signal on nodes A and B. However, inverters I
2
and I
3
hold nodes A and B at the previous potential level of the Din signal until the CLK signal switches to Vcch.
A problem arises when node A or B discharges to ground but nodes A or B hold an opposite potential level from the previous cycle. For example, when the CLK signal switches from zero to Vcch, transistor N
3
turns on and node A discharges to ground. However, if node A holds the Vcch potential, discharging to ground would cause a charge contention, leading to poor performance.
Further, since node A or B discharges to ground through a number of transistors, either N
1
and N
3
or N
2
and N
3
, latch
100
may introduce unnecessary delay between the Din signal and the Dout signal.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need for an improved level converting latch.
REFERENCES:
patent: 4996453 (1991-02-01), Zanders et al.
patent: 5382838 (1995-01-01), Sasaki et al.
patent: 5508648 (1996-04-01), Banik
patent: 5751174 (1998-05-01), Kuo et al.
patent: 5767716 (1998-06-01), Ko
patent: 5825205 (1998-10-01), Ohtsuka
patent: 5872476 (1999-02-01), Mihara et al.
patent: 5880617 (1999-03-01), Tanaka et al.
patent: 5929687 (1999-07-01), Yamauchi
patent: 5929688 (1999-07-01), Ueno et al.
patent: 6011421 (2000-01-01), Jung
patent: 6211713 (2001-04-01), Uhlmann
patent: 6225846 (2001-05-01), Wada et al.
patent: 6456136 (2002-09-01), Sutherland et al.
Kawaguchi, H., et al., “A CMOS Scheme for 0.5V Supply Voltage with Pico-Ampere Standby Current”,ISSCC, IEEE 1998, Slide Supplement, 154-155, 12.4.--1-12.4-4, (1998).
Kuroda, T., et al., “A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme”,IEEE Journal of Solid-State Circuits, vol. 31, 1770-1779, (Nov. 1996).
Usami, K., et al., “Automated Low-Power Technique Exploiting Multiple Supply Voltages Applied to a Media Processor”,IEEE Journal of Solid-State Circuits, vol. 33, 463-471, (Mar. 1998).
Chatterjee Bhaskar P.
Hsu Steven K.
Krishnamurthy Ram K.
Lam Tuan T.
Nguyen Long
Schwegman Lundberg Woessner & Kluth P.A.
LandOfFree
Level converting latch does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Level converting latch, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Level converting latch will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3035635