Level converting circuit

Details Level converting circuit Level converting circuit

1992-01-13

1993-08-17

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307567, H03K 501, H03K 502

Patent

active

052372120

ABSTRACT:
A level converting circuit for converting input signals into different level signals which enables a stable high speed operation to be realized and which may be used advantageously for driving, above all, liquid crystal display devices. Voltage clamping circuits 1 and 2 are provided at signal input terminals of n-MOS transistors 3 and 4 connected to the drains of pMOS transistors 5 and 6 connected in a current mirror configuration. By these voltage clamping circuits 1 and 2, the input levels of the nMOS transistors 3 and 4 are shifted to higher levels, as a result of which a current larger than that in the conventional circuit flows through the nMOS transistors 3 and 4 to speed up charging and discharging. Stable driving may be enabled even when the nMOS transistors 3 and 4 are formed as thin film field effect transistors for use with liquid crystal display elements.

REFERENCES:
patent: 4486670 (1984-12-01), Chan et al.
patent: 4713600 (1987-12-01), Tsugaru et al.

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