Level converter with delay circuitry used to increase switching

Details Level converter with delay circuitry used to increase switching Level converter with delay circuitry used to increase switching

1992-10-16

1994-05-31

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, H03K 190185, H03K 190948

Patent

active

053172132

ABSTRACT:
A level converting circuit has a function of converting an input signal of a first logic level into an output signal of a second logic level. The level converting circuit includes a first transistor responsive to an input signal IN for charging an output node to the ground potential, a second transistor responsive to the input signal IN for lowering the potential of the output node to the negative potential VEE, a third transistor responsive to the potential of the output node for controlling operations of the second transistor, and fourth and fifth transistors responsive to a delay signal with delay to an output of the level converting circuit for controlling the amount of current flowing through the output node. An inverted, amplified signal of the output node is applied to the gate of the fourth transistor, and a non-inverted, amplified signal of the output node is applied to the gate of the fifth transistor. The fourth and the fifth transistors serve to enhance the potential change of the output node by the delay signal (amplified signal). As a result, a level converting circuit carrying out a switching operation at a high speed in response to the input signal IN can be implemented.

REFERENCES:
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"A 5-ns 1-Mb ECL BiCMOS SRAM", by M. Takada et al., IEEE Journal of Solid-State Circuits, vol. 25, No. 5, Oct. 1990, pp. 1057-1062.

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