Computer graphics processing and selective visual display system – Display driving control circuitry
Reexamination Certificate
2001-02-12
2003-07-15
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Display driving control circuitry
C345S098000
Reexamination Certificate
active
06593920
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a level converter circuit and a liquid crystal display device employing the level converter circuit, and in particular to a level converter circuit formed by polysilicon transistors.
Liquid crystal display modules of the STN (Super Twisted Nematic) type or the TFT (Thin Film Transistor) type are widely used as a display device for a notebook personal computer and the like. Some driver circuits for driving such liquid crystal display panels need a level converter circuit external to the liquid crystal display panel. Such a level converter circuit is disclosed in Japanese Patent Application Laid-open No. Hei 6-204,850 (laid-open on Jul. 22, 1994), for example.
FIG. 13
is a circuit diagram of an example of a prior art level converter circuit. The level converter circuit shown in
FIG. 13
is formed by MOS transistors using single crystal silicon for their semiconductor layers, and is of the same circuit configuration as that shown in
FIG. 4
of Japanese Patent Application Laid-open No. Hei 6-204,850.
The level converter circuit shown in
FIG. 13
has a CMOS inverter INV
1
to which a low-voltage input signal &phgr;
1
is supplied and a CMOS inverter INV
2
to which an output signal &phgr;
2
from the CMOS inverter INV
1
is supplied.
The CMOS inverter INV
1
is formed by a p-channel MOS transistor (hereinafter referred to as a PMOS) M
5
and an n-channel MOS transistor (hereinafter referred to as an NMOS) M
6
which are connected in series between a low voltage VCC and a reference voltage (or ground potential) Vss.
The CMOS inverter INV
2
is formed by a PMOS M
7
and an NMOS M
8
which are connected in series between the low voltage VCC and the reference voltage (or ground potential) Vss.
Further, the level converter circuit includes a series combination of a PMOS M
9
and an NMOS M
11
and a series combination of a PMOS M
10
and an NMOS M
12
, which are connected between a high voltage VDD and the reference voltage VSS.
An output signal &phgr;
3
from the CMOS inverter INV
2
is supplied to a gate electrode of the NMOS M
11
, and an output signal &phgr;
2
from the CMOS inverter INV
1
is supplied to a gate electrode of the NMOS M
12
. A gate electrode of the PMOS M
9
is connected to a drain electrode of the PMOS M
10
, and a gate electrode of the PMOS M
10
is connected to a drain electrode of the PMOS M
9
.
The input signal &phgr;
1
supplied via an input terminal VIN has an amplitude between the low voltage VCC and the reference voltage VSS, and is converted into the low voltage outputs &phgr;
2
and &phgr;
3
each having amplitudes between the low voltage VCC and the reference voltage VSS.
The low voltage output signals &phgr;
2
and &phgr;
3
are supplied to gate electrodes of the NMOS M
11
and the NMOS M
12
, respectively, and outputs from output terminals VOUT
1
and VOUT
2
are two level-converted signals, that is, two complementary output signals &phgr;
4
and &phgr;
5
having amplitudes between the high supply voltage VDD and ground potential VSS, respectively.
For example, suppose that the low voltage output signal &phgr;
2
is at a high level (hereafter referred to merely as an H level) and the low voltage output signal &phgr;
3
is at a low level (hereafter referred to merely as an L level). Then the NMOS M
12
is ON, PMOS M
9
is ON, NMOS M
11
is OFF, and PMOS M
10
is OFF, and therefore the output terminal VOUT
2
outputs the ground potential VSS and the output terminal VOUT
1
outputs the high voltage VDD.
Next, suppose that the low voltage output signal &phgr;
2
is at the L level and the low voltage output signal &phgr;
3
is at the H level. Then the NMOS M
12
is OFF, the PMOS M
9
is OFF, the NMOS M
11
is ON, and the PMOS M
10
is ON, and therefore the output terminal VOUT
2
outputs the high supply voltage VDD and the output terminal VOUT
1
outputs the ground potential VSS.
FIG. 14
is a circuit diagram of another example of a prior art level converter circuit. The level converter circuit shown in
FIG. 14
is also formed by MOS transistors using single crystal silicon for their semiconductor layers, and is of the same circuit configuration as that shown in
FIG. 1
of Japanese Patent Application Laid-open No. Hei 6-204,850.
The level converter circuit shown in
FIG. 14
differs from that shown in
FIG. 13
, in that the CMOS inverter INV
2
is omitted, the output signal &phgr;
2
from the CMOS inverter INV
1
is supplied to the source electrode of the NMOS M
11
, and the gate of which is supplied with the low voltage VCC.
In the level converter circuit shown in
FIG. 13
, when the level-converted output signals &phgr;
4
, &phgr;
5
from the output terminals VOUT
1
, VOUT
2
change from the H level to the L level, or from the L level to the H level, all of the PMOS M
9
, the NMOS M
11
, the PMOS M
10
and the NMOS M
12
are turned ON simultaneously, and consequently, currents flow through a series combination of the PMOS M
9
and the NMOS M
11
and a series combination of the PMOS M
10
and the NMOS M
12
, respectively. The level converter circuit shown in
FIG. 14
is configured so as to prevent such currents from flowing through the series combination of the PMOS M
9
and the NMOS M
11
and the series combination of the PMOS M
10
and the NMOS M
12
.
The level converter circuit shown in
FIG. 13
needs a total of eight MOS transistors comprising four MOS transistors M
5
to M
8
in the low-voltage circuit and four MOS transistors M
9
to M
12
in the high-voltage circuit, the level converter circuit shown in
FIG. 14
needs six MOS transistors, and therefore the prior art level converter circuits had the problem in that many MOS transistors are needed.
It is known that mobility in MOS transistors using as their semiconductor layers, single crystal silicon, polysilicon and amorphous silicon are 1,000 to 2,000 cm
2
/(V·s), 10 to 100 cm
2
/(V·s), and 0.1 to 10 cm
2
/(V·s), respectively. MOS transistors using as their semiconductor layers, polysilicon and amorphous silicon are capable of being fabricated on a transparent insulating substrate made of quartz glass or glass having a softening temperature not higher than 800° C., and therefore electronic circuits can be fabricated directly on a display device such as a liquid crystal display device.
FIG. 15
is a graph showing an example of switching characteristics of an n-channel MOS transistor having a semiconductor made of single crystal silicon, and
FIG. 16
is a graph showing an example of switching characteristics of an n-channel MOS transistor having a semiconductor layer made of polysilicon.
In
FIGS. 15 and 16
, curves A represent characteristics for a standard threshold VTH, curves B represent characteristics for a threshold voltage VTH shifted by −1 V from the standard threshold voltage, and curves C represent characteristics for a threshold voltage VTH shifted by +1 V from the standard threshold voltage.
As is understood from
FIGS. 15 and 16
, in the case of the polysilicon MOS transistor (a polysilicon thin film transistor, for example) using as a semiconductor layer a polysilicon obtained by a solid phase epitaxy method crystallizing at a temperature of 500° C. to 1,100° C., or a polysilicon obtained by crystallizing by laser-annealing amorphous silicon produced by a CVD method, when a gate-source voltage VGS is small (5 V or less), drain currents ID of the polysilicon MOS transistor is smaller than those of the MOS transistor having the semiconductor layer of single crystal silicon, and drain currents ID of the polysilicon MOS transistor vary greatly with variations of the threshold voltages VTH.
As a result, when the level converter circuits shown in
FIGS. 13 and 14
are formed by MOS transistors having semiconductor layers made of single crystal silicon, satisfactory operation can be guaranteed, but when the level converter circuits shown in
FIGS. 13 and 14
are formed by polysilicon MOS transistors having semiconductor layers made of polysilicon, there was a disadvantage that sufficient driving capability coul
Ode Yukihide
Okumura Haruhisa
Eisen Alexander
Hitachi , Ltd.
Hjerpe Richard
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