Level converter circuit

Details Level converter circuit Level converter circuit

2000-10-30

2003-12-09

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C327S103000, C327S112000, C326S081000

Reexamination Certificate

active

06661274

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a level converter circuit, and in particular, to a differential signal output level converter circuit which outputs a differential signal.
BACKGROUND OF THE INVENTION
In recent years, the process technology is progressing, and thereby, there are many cases where different potential signals must be handled, or a differential signal is used in order to propagate a high speed signal. For this reason, a differential signal output circuit and a level converter circuit are both required. However, if these circuits are included then the circuit scale increases. When many circuits are operated in synchronous with one clock signal, it is desirable that a skew between these circuits is small as much as possible. In order to make small the skew, a circuit scale needs to be made small as much as possible so as to make small a propagation delay time of the circuit itself.
FIG. 1
is a circuit diagram showing a construction of a conventional differential signal output circuit comprising a CMOS circuit. This differential signal output circuit comprises four inverters
11
,
12
,
13
and
14
, and a through circuit
15
.
The first inverter
11
uses a signal from an input terminal
10
as an input signal. A signal outputted from the first inverter
11
is input into the second inverter
12
and the third inverter
13
. An output signal of the second inverter
12
is output to a first output terminal
16
via the through circuit
15
. A signal output from the third inverter
13
is input into the fourth inverter
14
. An output signal of the fourth inverter
14
is output to a second output terminal
17
.
When the potential level of the input signal is relatively low (hereinafter, referred to as L level), output potential of the first inverter
11
becomes a relatively high potential level (hereinafter, referred to as H level). The output potentials of the second inverter
12
and the third inverter
13
both become L level. Moreover, potential level of the fourth inverter
14
becomes H level. Thus, the output potential level of the first output terminal
16
and the output potential level of the second output terminal
17
become L level and H level, respectively. On the other hand, when the input signal is H level, the output potential levels become reverse to the above case. Accordingly, the signal goes through a three-stage logical element or transistor from the input terminal
10
to the output terminals
16
and
17
.
FIG. 2
is a circuit diagram showing another construction of the conventional differential signal output circuit comprising a CMOS circuit. This differential signal output circuit comprises four inverters
21
,
22
,
23
and
24
, two N-channel MOS transistors (hereinafter, referred to as NMOS transistor) Q
1
and Q
2
, and two P-channel MOS transistors (hereinafter, referred to as PMOS transistor) Q
3
and Q
4
.
Input signal is input into the first inverter
21
via an input terminal
20
. A signal output from the first inverter
21
is input into the second inverter
22
and the third inverter
23
, and also input into the gates of source follower type second NMOS transistor Q
2
and second PMOS transistor Q
4
. The source of the second NMOS transistor Q
2
and that of the second PMOS transistor Q
4
are connected to a first output terminal
26
together with an output terminal of the second inverter
22
.
A signal output from the third inverter
23
is input into the fourth inverter
24
, and also input into the gates of source follower type first NMOS transistor Q
1
and first PMOS transistor Q
3
. The sources of the first NMOS transistor Q
1
and the first PMOS transistor Q
3
are connected to a second output terminal
27
together with an output terminal of the fourth inverter
24
.
When the input signal is L level, output potential of the first inverter
21
becomes H level. Therefore, output potential of the second inverter
22
becomes L level, and thus, L level signal is output to the first output terminal
26
. Moreover, the NMOS transistor Q
1
is turned on, and thereby, the potential level of the second output terminal
27
becomes H level. On the other hand, when the input signal is H level, the output potential of the first inverter
21
becomes L level. The output level is inverted by the second inverter
22
; therefore, the potential level of the first output terminal
26
becomes H level. Moreover, the PMOS transistor Q
3
is turned on, and thereby, the potential level of the second output terminal
27
becomes L level. Accordingly, the signal goes through a two-stage logical element or transistor from the input terminal
20
to the output terminals
26
and
27
.
FIG. 3
is a circuit diagram showing a construction of a conventional level converter circuit comprising a CMOS circuit. This level converter circuit comprises two inverters
31
and
32
, two NMOS transistors Q
5
and Q
6
, and two PMOS transistors Q
7
and Q
8
.
Input signal is input into the first inverter
31
via an input terminal
30
. A signal output from the first inverter
31
is input into the second inverter
32
, and also input into the gate of the first NMOS transistor Q
5
. Moreover, a signal output from the second inverter
32
is input into the gate of the second NMOS transistor Q
6
. The inverters
31
and
32
both output either a reference potential VSS or a first power supply potential VDL.
Drain of the first NMOS transistor Q
5
and drain of the first PMOS transistor Q
7
are connected in common, and, drain common to the above both transistors is connected to the gate of the second PMOS transistor Q
8
. Moreover, drain of the second PMOS transistor Q
8
and drain of the second NMOS transistor Q
6
are connected in common, and, drain common to the above both transistors is connected to the gate of the first PMOS transistor Q
7
, and further, is connected to the output terminal
36
. Source potential of NMOS transistor Q
5
and Q
6
is reference potential VSS. And source potential of PMOS transistor Q
7
and Q
8
is second power supply potential VDH.
When the input signal is L level, output potential of the first inverter
31
becomes H level. Therefore, the NMOS transistor Q
5
is turned on, and thereby, the second PMOS transistor Q
8
is turned on. Accordingly, H level signal is input into the output terminal
36
. On the other hand, where an input signal is H level, the output potential of the first inverter
31
becomes L level; therefore, output potential of the second inverter
32
becomes H level. Whereby the second NMOS transistor Q
6
is turned on; thus, L-level signal is output to the output terminal
36
. Accordingly, the signal goes through a three-stage logical element or transistor from the input terminal
30
to the output terminal
32
.
If the differential signal output circuit shown in FIG.
1
and the level converter circuit shown in
FIG. 3
are combined, a signal goes through three-stages in the differential signal output circuit, and three-stages in the level converter circuit. That is, the signal goes through six-stages of logical element or transistor in total from the input terminal
10
to the output terminal
36
. On the other hand, if the differential signal output circuit shown in FIG.
2
and the level converter circuit shown in
FIG. 3
are combined, a signal goes through two-stages in the differential signal output circuit, and three-stages in the level converter circuit. That is, the signal goes through five-stages of logical element or transistor in total from the input terminal
20
to the output terminal
36
.
In order to make the propagation delay time of the circuit small, and also to make the skew between a plurality of circuits small as much as possible, it is desirable to reduce the number of stages of logical element or transistor through which a signal goes in the differential signal output circuit and the level converter circuit.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a level converter circuit which has both functions of the differential s

Affiliated with

Also associated with

Rating

Level converter circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Level converter circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Level converter circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3182088