Level converter circuit

Details Level converter circuit Level converter circuit

1985-07-05

1987-09-29

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307446, 307450, 307264, 330300, H03K 19092, H03K 19086, H03K 19003, H03K 1710

Patent

active

046971092

ABSTRACT:
Herein disclosed is a circuit for converting the logic amplitude of an ECL by logically amplifying a TTL or CMOS so that no substantial dc current flows in the steady state. The level converting circuit comprises: a level-shift circuit for generating a first output with a small level-shift and a second output with a larger level-shift than said first output; a CMOS circuit including a PMOS transistor having its gate fed with said first output, and an nMOS transistor having its gate fed with said second output; and a current switch for giving output levels to turn on said PMOS transistor and off said nMOS transistor at its high level and to turn on said PMOS transistor and off said nMOS transistor at its low level.

REFERENCES:
patent: 3823330 (1974-07-01), Rapp
patent: 4321491 (1982-03-01), Atherton et al.
patent: 4326136 (1982-04-01), LeCan et al.
patent: 4453095 (1984-06-01), Wrathall

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