Level conversion input circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307443, H03K 19094, H03K 19017, H03K 19092

Patent

active

045636010

ABSTRACT:
An input circuit is provided for converting an ECL level to a CMOS level. The input circuit of the invention includes a first input circuit having at least a P-type MOSFET and an N-type MOSFET connected in series. The gate of the P-type MOSFET is connected to the input of the circuit for receiving an input signal of the ECL level and the output of the circuit is taken out from between both MOSFETs. A voltage generation circuit is also provided for applying a voltage to the gate of the N-type MOSFET of the first input circuit to control the logic threshold voltage of the first input circuit. The voltage generation circuit includes a second circuit, which receives a logic threshold voltage of ECL as its input and is equivalent to the first input circuit, and an amplification circuit of at least one stage which receives the output of the second input circuit and the logic threshold voltage of CMOS as its input and amplifies the difference between them.

REFERENCES:
patent: 4023050 (1977-05-01), Fox et al.
patent: 4150308 (1979-04-01), Adlhoch
patent: 4242604 (1980-12-01), Smith
patent: 4453095 (1984-06-01), Wrathall
Hoffman, "Positive Voltage Translation Circuit", IBM Tech. Discl. Bull.; vol. 17, No. 8, pp. 2392-2393; 1/75.

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