Level conversion circuit and semiconductor integrated circuit

Details Level conversion circuit and semiconductor integrated circuit Level conversion circuit and semiconductor integrated circuit

1997-03-14

1999-03-09

Callahan, Tim

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

327 55, 327215, 327434, 326 80, 326 81, H03K 19017

Patent

active

058806172

ABSTRACT:
A level conversion circuit comprises a first CMOS circuit connected between a high voltage (5 V: VDD) power supply and ground to receive an input signal IN1 having an amplitude between a low voltage (3 V: VCC) and a ground voltage (0 V), a second CMOS circuit connected between the 5 V power supply and ground to output an output signal OUT1 having an amplitude between 5 V and 0 V, and first and second intermediate circuits cross-connected between the first and second CMOS circuits. All MOS transistors constituting these circuits have the gate oxide films whose allowable breakdown voltage is lower than 5 V and higher than 3 V.

REFERENCES:
patent: 4103190 (1978-07-01), Beutler
patent: 5300832 (1994-04-01), Roger
patent: 5436585 (1995-07-01), DiMarco
patent: 5534798 (1996-07-01), Phillips et al.
patent: 5619150 (1997-04-01), Briner

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