Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Utilizing three or more electrode solid-state device
Reexamination Certificate
2002-12-17
2004-04-06
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Utilizing three or more electrode solid-state device
C326S031000, C326S081000
Reexamination Certificate
active
06717456
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to the field of level conversion circuit technology; in particular, it pertains to a bidirectional level conversion circuit.
BACKGROUND OF THE INVENTION
The integration density of ICs for electronic equipment systems is increasing, with corresponding reductions in the power supply voltages used. For example, with the advent of LSI, a system which formerly operated with a 5V power supply came to require only a low-voltage power supply, such as 3.3V or 2.5V. Furthermore, in recent years, it has become more common with ICs to use several power supply voltages. With such a system, it is necessary to apply a level conversion to a 5V signal to obtain a low-voltage signal of 3.3V, or to apply level conversion to a low-voltage signal of 3.3V to obtain 5V, for example.
This type of conversion can be achieved using a variety of methods, and special logic ICs for level conversion are also available.
Reference numeral
101
in
FIG. 3
indicates an example level conversion circuit which uses a pass transistor
102
from an N-channel MOS transistor out of the internal circuit of a logic IC of the prior art.
In said level conversion circuit
101
, the gate terminal of pass transistor
102
is connected to power supply voltage line C via diode
103
, and pass transistor
102
is turned on by power supply voltage V
CC
from power supply voltage line C. When the voltage at the gate terminal with respect to the source terminal is denoted as gate voltage V
tn
, voltage V
B
at port B serving as the source terminal will be lower than voltage V
s0
of the gate terminal by gate voltage (threshold voltage) V
tn
regardless of the level of voltage V
A
at port A serving as a drain terminal.
That is, voltage V
B
at port B is restricted to (voltage V
S0
of gate terminal−gate voltage V
tn
) as long as voltage V
A
of port A is higher than voltage V
B
of port B.
For example, as long as the voltage of port terminal A is 3.3V or higher, a voltage V
B
=3.3V can be generated by level-converting voltage V
A
at port A if V
tn
=1.0V, and voltage V
S0
at gate terminal is 4.3V to give an output of 3.3V voltage at port B. Therefore, even if voltages of 5V and 3.3V must both be handled in terms of interfacing with the bus, both voltages can be handled by keeping pass transistor
102
conductive.
Also, because the propagation of a signal from port A to port B can be shut off by bringing voltage V
S0
of the gate terminal to the GND level and disconnecting pass transistor
102
, hot-line attachment/detachment function of the bus can be realized effectively. The delay time of a signal from port A to port B can be made small enough to be ignored by reducing the on-resistance of pass transistor
102
.
While the level conversion circuit
101
is capable of high level to low level conversion, it is incapable of low level to high level conversion. When it is used for interfacing with a bus, there are many cases which require bidirectional level conversion.
Reference numeral
111
in
FIG. 4
shows an example of such a level conversion circuit, where the configuration is identical to that of level conversion circuit
101
in
FIG. 3
, except that port A is pulled up to the level of high voltage power supply terminal D with pull-up resistor
115
.
Here, too, in the case of said level conversion circuit
111
, assuming that the voltage on the gate terminal of pass transistor
102
is V
S0
, pass transistor
102
turns off if voltage V
B
at port B is greater than or equal to V
S0
−V
tn
. As a result, high power supply voltage V
CCH
is applied at port A via pull-up resistor
115
. If high power supply voltage V
CCH
is 5.0V, and voltage V
B
at port B is 3.3V, voltage V
A
at port A is 5.0V, which means that the low voltage signal of 3.3V has been level-converted to a high voltage signal of 5.0V.
Although capable of bidirectional level conversion between ports A and B, said level conversion circuit
111
has the following shortcomings.
(1) When voltage V
A
at port A changes from low level to high level as voltage V
B
at port B is propagated to port A, said change in voltage is regulated in accordance with a time constant determined on the basis of the resistance of pull-up resistor
115
and the load capacitance of port A at the point where the level of voltage V
A
has become greater than V
S0
−V
tn
, so that the change is subject to a delay. Therefore, the circuit cannot follow high-frequency signals.
(2) When voltage V
A
at port A is at the low level, there is a continuous large current flow into pull-up resistor
115
.
(3) Because pull-up resistor
115
is outside to level conversion circuit
111
, that is, an extra part is needed, extra real estate is required.
A general object of the present invention is to present a power-saving and space-saving level conversion circuit capable of bidirectional level conversion even for high-frequency signals.
SUMMARY OF THE INVENTION
In order to solve the problems, the level conversion circuit of one aspect of the present invention is provided with a first port to which a first logic level signal is applied, a second port to which a second logic level signal is applied, which has a logic level lower than the first logic level, a transistor connected between the first and the second ports, a first switching circuit which is connected between a power supply terminal to which a power supply voltage corresponding to the first logic level is applied and the first port and becomes conductive according to the first port level, and a second switching circuit which is connected between the power supply terminal to which the power supply voltage corresponding to the first logic level is applied and the first port and becomes conductive together with the first switching circuit only for a prescribed period, wherein a signal having different levels can be propagated from the first port to the second port or from the second port to the first port.
In one aspect of the present invention, it is desirable that the resistance be greater when the first switching circuit is conductive than when the second switching circuit is conductive. Preferably, it is provided with a pulse generator which generates a pulse signal used for temporarily turning on the second switching circuit in accordance with changes in the logic level of the first port.
In addition, in one aspect of the present invention, it is desirable that the pass transistor and the first and the second switching circuits be configured with MOS transistors. Preferably, in accordance with an aspect of the present invention, the transistor is an NMOS transistor, and a voltage higher than a power supply voltage corresponding to the second logic level by an amount equivalent to the threshold voltage of said NMOS transistor is applied to the gate terminal of the NMOS transistor.
Furthermore, it is desirable, according to another aspect of the invention, that it be provided with a NAND gate having 2 input terminals respectively connected to the first port and an enable signal application terminal and a power supply circuit configured with a diode and a resistor connected in series between the power supply terminal to which the power supply voltage corresponding to the first logic level is supplied and a power supply terminal to which a reference voltage is supplied, where the first and the second switching circuits are respectively configured with first and second PMOS transistors, the first pulse generator is configured with a resistor and a capacitor connected in series between the power supply terminal to which the power supply voltage corresponding to the first logic level is supplied and the output terminal of the NAND gate, and the gate terminal of the first PMOS transistor is connected to the output terminal of the NAND gate, the gate terminal of the second PMOS transistor is connected to the midpoint of the connection node between the resistor and the capacitor of the pulse generator, the gate terminal of the NMOS transistor is connected to the midpo
Brady III W. James
Kempler William B.
Le Dinh T.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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