Level and edge sensitive input circuit

Details Level and edge sensitive input circuit Level and edge sensitive input circuit

1989-03-27

1990-07-31

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307350, 307360, 3072722, H03K 520

Patent

active

049452614

ABSTRACT:
A level and edge sensitive input circuit can recognize a variety of types of input signals on an input line and provide a standard digital logic output for use within the equipment. The input circuit is formed from a bias circuit, two comparators, and a memory bit. The bias circuit applies a bias voltage to the input line. A first comparator inverts the state of the memory bit when the input signals are an increment above the bias voltage. The second comparator clears the state of the memory bit when the input signals are an increment below the bias voltage. In this way, the memory bit cycles through states which provide the desired output signals for use within the equipment.

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Viles, Upper and Lower Threshold Can Be Set Independently in Latching-Comparator Circuit, 12-20-77, Electronic Design 26, pp. 176.

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