Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
Reexamination Certificate
2011-04-26
2011-04-26
Lin, Sun J (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Physical design processing
C716S118000, C716S122000, C716S123000, C716S124000
Reexamination Certificate
active
07934188
ABSTRACT:
A hierarchical method of legalizing the placement of logic cells in the presence of blockages selectively classifies the blockages into at least two different sets based on size (large and small). Movable logic cells are relocated first among coarse regions between large blockages to remove overlaps among the cells and the large blockages without regard to small blockages (while satisfying capacity constraints of the coarse regions), and thereafter the movable logic cells are relocated among fine regions between small blockages to remove all cell overlaps (while satisfying capacity constraints of the fine regions). The coarse and fine regions may be horizontal slices of the placement region having a height corresponding to a single circuit row height of the design. Cells are relocated with minimal perturbation from the previous placement, preserving wirelength and timing optimizations. The legalization technique may utilize more than two levels of granularity with multiple relocation stages.
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Alpert Charles J.
Dotson Michael W.
Nam Gi-Joon
Ramji Shyam
Viswanathan Natarajan
Handelsman Libby Z.
International Business Machines - Corporation
Lin Sun J
Musgrove Jack V.
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