LED matrix control system with Field Programmable Gate Arrays

Details LED matrix control system with Field Programmable Gate Arrays LED matrix control system with Field Programmable Gate Arrays

1999-11-15

2002-12-03

Nguyen, Chanh (Department: 2675)

Computer graphics processing and selective visual display system

Plural physical display element control system

Segmented display elements

C345S082000

Reexamination Certificate

active

06489937

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of controlling the individual LED's in a matrix of LED's, and in particular to a system using two field programmable gate arrays (FPGA).
BACKGROUND OF THE INVENTION
In many electronic devices, an LED matrix is used to display information regarding the device. In a computer network devices, a central processing unit (CPU) often determines which LED's are to be on and off, and does this by writing a data word to a specific address. The data word indicates the state, on or off, and the address corresponds to a particular LED. Electronic components must then be used between the CPU and the LED matrix. These components must be able to convert the address and data information into specific electrical currents that energize or enable the individual LED's. The number of LED's in a matrix can vary, as well as the arrangement of the LED's in a matrix. As an example, an LED matrix of 36 LED's can be arranged in two rows with 18 columns, three rows with 12 columns, four rows with nine columns, and six rows with six columns. Therefore the components between the CPU and the LED matrix changes for each LED matrix having a different number of LED's, or having a different arrangement of LED's.
SUMMARY AND OBJECTS OF THE INVENTION
One of the objects of the present invention is to provide an LED matrix control system where the same component can be used for several differently sized and arranged LED matrixes. This object is accomplished by using an FPGA (Field Programmable Gate Array) in between the CPU and the LED matrix. The program for the FPGA is downloaded into the FPGA from the CPU at startup of the device.
It is another object of the present invention to reduce the size of the program for the FPGA, and to reduce the time needed to program the FPGA. The present invention accomplishes this object by using two FPGA's, where one FPGA controls a first set of LED's and the second FPGA controls a second set of LED's. The first set and the second set of LED's are preferably mutually exclusive.
In a preferred embodiment, the first FPGA controls all of the column lines of an LED matrix, and controls a sub set of the row lines of the LED matrix. The second FPGA also controls all of the column lines and controls another sub set of the row lines. Each FPGA receives the same information from the CPU. Each FPGA also has a config line. The config line of one FPGA is connected to a logical zero, such as ground, and the config line of the other FPGA is connected to a logical one, such as a power supply voltage. Each FPGA only enables or energizes one row at a time. The rows are energized on and off so quickly, that the human persistence of vision causes the appearance of the energized LED's to always appear lit.
Each FPGA includes a row control means which controls which rows are energized. The row control means in each FPGA is based on the same clock signal, preferably the clock signal coming from the CPU. From this clock signal, row signals are generated. Each row signal separately indicates which row is to be energized. Each FPGA generates a separate row signal for each of the rows in the LED matrix, regardless of whether the respective FPGA will control that row. Each of the row signals in each FPGA also generates an indication of when the respective row is to be enabled, regardless of whether the respective FPGA controls that row. Each FPGA also includes a time logic block which receives the row signals and generates row subset signals. The time logic block also receives the config signal. Based on the config signal, the time logic block chooses which of the row signals to include in the row subset signals. As an example, if the config signal is at a logical one level, the time logic block includes only the row signals for the first set of rows in the row subset signals. If the config signal is at a logical zero level, the time logic block includes only the row signals for the second set of rows in the row subset signals.
Each FPGA also includes an LED register array and generates individual LED signals for each of the LED's in the LED matrix based on the information received from the CPU. Each LED register array receives the same signals from the CPU. Each LED register array also receives the config signal. Based on the config signal, each LED register array generates the individual LED signals for either the first or second set of rows in the LED matrix.
In order to enable or energized one LED, the row and column lines for that one LED must be enable. When one of the row subset signals is enabled in an FPGA, the FPGA enables the respective row. When one of the individual LED signals is enabled in an FPGA, and the row subset signal of that one individual LED is also enabled, the FPGA enables the column line for that one individual LED. In this way, all of the LED's and in an LED matrix can be individually and separately controlled by two or more FPGA's which have identical programming, and can be programmed in parallel to reduce programming time. Also the size of the FPGAs can be smaller and it is often more cost-effective to use two smaller FPGA's then one large FPGA. The present invention is therefore able to provide an LED matrix control system which is simple in design, reliable during operation and economical to manufacture.
The various features of novelty which characterize the invention are pointed out with particularity in the claims annexed to and forming a part of this disclosure.
For a better understanding of the invention, its operating advantages and specific objects attained by its uses, reference is made to the accompanying drawings and descriptive matter in which preferred embodiments of the invention are illustrated.


REFERENCES:
patent: 5574930 (1996-11-01), Halverson et al.
patent: 5603043 (1997-02-01), Taylor et al.
patent: 5903624 (1999-05-01), Boswell et al.
patent: 6058263 (2000-05-01), Voth

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