Least significant bit and guard bit extractor

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36471504, G06F 501

Patent

active

058416838

ABSTRACT:
In connection with a logic circuit including a mask generator for determining a value for a so-called "sticky bit" in a binary number to be truncated and rounded, an intermediate signal is taken from the mask generator and an Exclusive-OR function applied to adjacent bits to generate a second mask containing or adjacent to a transition between the portion of the number to be dropped and the portion to be retained in the truncated number. The second mask is applied to different overlapping groups of bits in a portion of the number which contains the least significant bit and the guard bit as determined from the number of bits to be dropped, for example, by shifting out from a shifter, as the number is truncated and rounded to extract a specific bit in each group of bits. By extracting such specific bits using a mask, the extraction process is removed from the critical path of the processor which includes the shifter and the extraction process can proceed in parallel with the shifting process.

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