Least recently used arbiter with programmable high priority mode

Details Least recently used arbiter with programmable high priority mode Least recently used arbiter with programmable high priority mode

1988-12-21

1990-08-28

Zache, Raulfe B.

Boots, shoes, and leggings

3642426, 3642428, G06F 1314

Patent

active

049530810

ABSTRACT:
In a data bus system which links a plurality of users, user access to the bus is provided by an arbiter which responds to a plurality of user requests for bus access by employing an adjustable priority scheme for granting access. When a user has access to the bus, the arbiter updates user priority by assigning the lowest priority to the current user and upwardly adjusting the priorities of all currently-requesting users.

REFERENCES:
patent: 4611297 (1986-09-01), Dudley et al.
patent: 4789926 (1988-12-01), Clarke
IEE Reprint Performance Analysis of High-Speed Digital Buses for Multiprocessing Systems, by W. L. Bain, Jr. and S. R. Ahuja, Bell Laboratories, 1981, pp. 107-133.

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