Multiplex communications – Pathfinding or routing – Through a circuit switch
Reexamination Certificate
1998-03-19
2001-10-30
Vu, Huy D. (Department: 2735)
Multiplex communications
Pathfinding or routing
Through a circuit switch
C370S392000, C370S390000
Reexamination Certificate
active
06310874
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
NOT APPLICABLE
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
NOT APPLICABLE
BACKGROUND OF THE INVENTION
The present invention is generally related to network switches, and more particularly to address learning operations for multicast data units.
Network switches commonly employ an address table to facilitate the flow of data units in a network. The address table includes entries that indicate address information for various devices that are coupled with the network such as other switches, computers and printers. The address information indicates which port or ports in the switch should be employed for forwarding the data unit to a particular device in the network. Following receipt of the data unit the switch attempts to locate an entry in the address table that pertains to the destination address specified in the data unit header. If a pertinent entry is located in the address table then the information contained in that entry is employed to identify the port or ports for “forwarding” of the data unit. If a pertinent entry cannot be located in the address table then the switch may “flood” the data unit by transmitting the data unit through every port except the port on which the data unit was received. Hence, network and switch bandwidth is conserved if a pertinent entry is available in the address table.
It is known to update the address table by “learning” new address information for unicast transmissions. Each data unit includes a header portion with a source address field and a destination address field. Address information can be learned by employing the source address specified in the data unit header. If a first data unit is transmitted from a first device to a second device via the switch, and the switch does not have the address for the first device in its address table, then upon the initial transmission from the first device to the second device, the switch learns the address. If address information for the second device is also unknown, the switch floods the first data unit in order to accomplish transmission to the second device. If the second device responds by transmitting a second data unit back to the first device via the switch then the switch learns the address of the second device from the source address field of the second data unit. The switch employs the address information that was previously learned from the first device to “forward” the second data unit toward the first device via a single port. In a subsequent transmission from the first device to the second device the switch employs the learned address information for the second device to efficiently “forward” the data unit toward the second device via a single port without flooding the data unit through the network.
“Forwarding” can also be employed with multicast transmissions, e.g., where the first data unit is transmitted from the first device to a plurality of devices via the switch. However, the learning operation becomes more complex in the case of a multicast data unit. For example, determining a map of output ports for data unit forwarding is more difficult because calculations are made for each separate path upon which copies of the multicast data unit will be transmitted. Further, multicast traffic tends to be “bursty,” so the processor that enables multicast learning operations may be unable to install address information for multicast flows as quickly as the flows are established through the switch. As a result, more data units may be flooded from the switch, so bandwidth use is less efficient.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, in a switch having an address resolution processor for resolving multicast address information from a received data unit, transmission of data units to the address resolution processor is controlled to inhibit multiple data units from a single multicast flow from being enqueued with the address resolution processor. In one embodiment in which the switch includes a plurality of Input/Output Application Specific Integrated Circuits (“I/O ASICs”), each having one segment of a distributed address table and a plurality of ports, no more than one data unit from each I/O ASIC is permitted to be enqueued with the address resolution processor at any point in time.
A learn pending indicator may be employed to implement the described technique. A separate learn pending indicator may be defined for each I/O ASIC in the switch. When a first multicast data unit is received in one of the I/O ASICs, an address table lookup operation is performed based upon information such as a destination Media Access Control (“MAC”) address in the header of the multicast data unit. If a pertinent entry is found in the address table then the data unit is forwarded. If no pertinent entry is found in the address table, the state of the learn pending indicator associated with the I/O ASIC that received the data unit is determined. If the learn pending indicator is not set, i.e., no multicast data unit is enqueued with the processor for address resolution, then the first multicast data unit is enqueued with the address resolution processor. The address resolution processor facilitates an address learning operation by prompting a new entry that corresponds to the address information to be entered in each address table segment. If the learn pending indicator is set, i.e., a previous multicast data unit is enqueued with the address resolution processor, then the current multicast data unit is not enqueued with the address resolution processor. In either case the multicast data unit is flooded.
In one embodiment the learn pending indicator is periodically cleared to facilitate switch operation. Multicast data units that are enqueued with the address resolution processor from different I/O ASICs are all placed in a single FIFO queue that is associated with the address resolution processor. Other data units may also be placed in the FIFO queue. The learn pending bit limits buildup of multicast miss traffic in the FIFO queue to facilitate other processing by the address resolution processor. However, a recovery mechanism is also employed to determine when a multicast data unit provided to the FIFO queue has been missed, such as if the FIFO queue overflows. The learn pending indicator is reset after a predetermined number of data units has passed out of the FIFO queue or after a predetermined length of time to facilitate “loss frame recovery.” Hence, the learn pending bit is not permitted to become “stuck” in the ON position.
REFERENCES:
patent: 5923654 (1999-07-01), Schnell
patent: 5938736 (1999-08-01), Muller et al.
patent: 5946313 (1999-08-01), Allan et al.
Boxer Lawrence Aaron
Heiner, Jr. Edward A.
Miller David S.
3Com Corporation
Jones Prenell
Vu Huy D.
Weingarten, Schurgin Gagnebin & Hayes LLP
LandOfFree
Learn pending frame throttle does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Learn pending frame throttle, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Learn pending frame throttle will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2616522