Leakage mitigation logic

Details Leakage mitigation logic Leakage mitigation logic

2005-12-15

2008-11-04

Elms, Richard (Department: 2824)

Static information storage and retrieval

Powering

C365S227000, C365S229000

Reexamination Certificate

active

07447099

ABSTRACT:
Leakage current from a circuit for handling data is reduced using leakage control circuit operable in a leakage reduction mode. The data handling circuit comprises data handling logic operable to receive an input data value and to output and output data value. The data handling circuit also comprises a latch operable to latch the output data value in response to a clock signal having a clock period. Both the leakage control circuitry and the latch are controlled dependent upon the same clock signal and the leakage control circuitry is controlled such that it is in a leakage reduction mode for a time less than the clock period. This approach enables leakage reduction to be provided in circuits which are still operational and is particularly suited to data handling circuits that employ frequency scaling.

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Rao et al., “Circuit Techniques for Gate and Sub-Threshold Leakage Minimization in Future CMOS Technologies”, European Solid-State Circuits, 2003, ESSCIRC '03 Conference.

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