Leakage current correcting circuit

Details Leakage current correcting circuit Leakage current correcting circuit

1999-08-25

2001-06-05

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific input to output function

With compensation

C327S363000, C327S378000

Reexamination Certificate

active

06242966

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a semiconductor testing apparatus for testing a semiconductor device, and more particularly to a leakage current correcting circuit for reducing a leakage current in a programmable load circuit or the like which acts as a load for a device under test.
BACKGROUND ART
An electronic circuit on the test head of a semiconductor testing apparatus dedicated to input/output pins of a device under test (hereinafter referred to as “DUT”) is called pin electronics. The pin electronics comprises a driver for applying a predetermined signal to the pins of a DUT, a comparator for determining the level of a signal (High or Low) outputted from the DUT, and a programmable load circuit which acts as a load when a signal is outputted from the DUT.
A load condition for the programmable load circuit may be changed by a processor for controlling the entire semiconductor testing apparatus, and any load may be created as defined in the specifications of a DUT.
FIG. 1
is a circuit diagram showing an exemplary configuration of a programmable load circuit.
In
FIG. 1
, pin electronics comprise driver
3
, comparator
4
, and programmable load circuit
1
, to which DUT
2
is connected for conducting a test.
Programmable load circuit
1
comprises a diode bridge composed of four diodes D
3
-D
6
; first current source
14
and second current source
15
acting as loads for DUT
2
; programmable voltage source
20
for applying to the diode bridge threshold voltage Vth which serves as a decision standard for selecting first current source
14
or second current source
15
, both of which act as loads for DUT
2
; transistors Q
5
-Q
8
serving as switches for connecting first current source
14
and second current source
15
to the diode bridge or to a ground potential; first regulated voltage source
18
(negative voltage source) for discharging node A when programmable load circuit
1
is OFF; second regulated voltage source
19
(positive voltage source) for charging node B when programmable load circuit
1
is OFF; diode D
1
serving as a switch for connecting node A with first regulated voltage
18
; diode D
2
serving as a switch for connecting node B with second regulated voltage source
19
; ON/OFF signal source
11
for outputting a signal for controlling programmable load circuit
1
to turn ON/OFF; third current source
16
for drawing a voltage at node B into output voltage Vp of second regulated voltage source
19
when programmable load circuit
1
is OFF; fourth current source
17
for drawing a voltage at node A into output voltage Vm of first regulated voltage source
18
when programmable load circuit
1
is OFF; transistors Q
1
-Q
4
serving as switches for switching current paths of third current source
16
and fourth current source
17
; and first level shift circuit
12
and second level shift circuit
13
for driving transistors Q
1
-Q
8
in accordance with an output signal of ON/OFF signal source
1
.
The ON of programmable load circuit
1
refers to a state in which first current source
14
or second current source
15
is connected to DUT
2
as a load, whereas the OFF of programmable load circuit
1
refers to a state in which first current source
14
and second current source are respectively connected to the ground potential and no load is connected to DUT
2
.
Also, output voltage Vth of programmable voltage source
20
, output current I
1
of first current source
14
, and output current I
2
of second current source
15
are each variable, and are set to predetermined values with programming processing.
In such a configuration, when a signal is outputted from DUT
2
, the output of driver
3
is maintained in a high impedance state, and programmable load circuit
1
is set ON. Programmable load circuit
1
is ON/OFF controlled by an output signal of ON/OFF signal source
11
such that it turns ON when a signal at High level is outputted from ON/OFF signal source
11
.
When a signal at High level is outputted from ON/OFF signal source
11
, first level shift circuit
12
supplies a base current to transistors Q
1
and Q
6
, while second level shift circuit
13
supplies a base current to transistors Q
3
and Q
8
. At this time, transistors Q
2
, Q
4
, Q
5
, Q
7
are OFF, while transistors Q
1
, Q
3
, Q
6
, Q
8
turn ON.
When transistors Q
1
and Q
3
turn ON, third current source
16
and fourth current source
17
are connected to the ground potential through transistors Q
1
and Q
3
, respectively.
When a signal at High level is outputted from DUT
2
in such a state, current I
2
flows from DUT
2
to second current source
15
through diode D
6
since the output voltage of DUT
2
is a voltage higher than threshold voltage Vth.
On the other hand, when a Low level is outputted from DUT
2
, current I
1
flows from first current source
14
to DUT
2
through diode D
4
since the output voltage of DUT
2
is a voltage lower than threshold voltage Vth.
Therefore, a load connected to the output of DUT
2
is switched in accordance with its output voltage and the value of the load is determined by current value I
1
of first current source
14
and current value I
2
of second current source
15
.
Since programmable voltage source
20
, first current source
14
, and second current source
15
may respectively change their output values with programming processing, current values I
1
, I
2
, which act as loads, may be changed in accordance with the specifications of DUT
2
.
On the other hand, when DUT
2
is switched into a signal input state, a signal is outputted from driver
3
to DUT
2
, and the output of DUT
2
is set in a high impedance state. Additionally, since no load needs to be connected, programmable load circuit
1
is set OFF.
Programmable load circuit
1
turns OFF when a signal at Low level is outputted from ON/OFF signal source
11
. When a Low level is outputted from ON/OFF signal source
11
, first level shift circuit
12
supplies a base current to transistors Q
2
and Q
5
, while second level shift circuit
13
supplies a base current to transistors Q
4
and Q
7
. In this event, transistors Q
1
, Q
3
, Q
6
, Q
8
are OFF respectively, and transistors Q
2
, Q
4
, Q
5
, Q
6
turn ON respectively.
When transistors Q
2
and Q
4
turn ON, third current source
16
and node B are connected through transistor Q
2
to charge a parasitic capacitance at node B to (Vp plus forward voltage V
F
of diode D
2
).
Additionally, fourth current source
17
and node A are connected through transistor Q
4
to discharge a parasitic capacitance at node A to (Vm minus forward voltage V
F
of diode D
5
).
On the other hand, when transistors Q
5
, Q
7
turn ON, first current source
14
is connected to the ground potential through transistor Q
5
, while second current source
15
is connected to the ground potential through transistor Q
7
. Thus, connection of DUT
2
with first current source
14
and second current source
15
, which act as loads therefore, is disconnected.
In such a programmable load circuit and driver having the pin electronics, it is desirable that leakage current be smaller to provide more accurate testing in an output disabled state.
With programmable load circuit
1
shown in
FIG. 1
, leakage current I
leakage
is expressed as I
leakage
=I
D4
-I
D6
in the disabled state, i.e., when programmable load circuit
1
is OFF.
The programmable load circuit shown in
FIG. 1
is a circuit which sets the output in a high impedance state by backwardly biasing a diode or a transistor. When high speed diodes, transistors or the like are used in such a circuit, the leakage current is increased by backward biasing because of the general tendency that faster devices exhibit a lower backward withstand voltage.
For this reason, when the source current (current consumed) of DUT
2
is measured, leakage current of the pin electronics affects the respective pins of DUT
2
, causing a deterioration of the measuring accuracy of a semiconductor testing apparatus.
The present invention has been made to solve the afor

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