Leadless semiconductor package

Details Leadless semiconductor package Leadless semiconductor package

2006-07-31

2008-11-04

Hoang, Quoc D (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With dam or vent for encapsulant

C257S676000, C257SE23037

Reexamination Certificate

active

07446397

ABSTRACT:
A leadless semiconductor package includes a lead frame, an adhesive, a chip, a plurality of first electrically conductive wires and a plurality of second electrically conductive wires. In this case, the lead frame has a chip paddle, a plurality of leads surrounding the chip paddle. The chip paddle has a cavity and a grounding area surrounding the cavity. The cavity has an opening, a bottom and a through hole, and the bottom is larger than the opening in size. The adhesive is disposed in the cavity. The chip have an active surface and a back surface opposed to the active surface, and the back surface is disposed in the cavity and is attached to the lead frame through the adhesive. The first electrically conductive wires electrically connect the leads and the chip. The second electrically conductive wires electrically connect the grounding area and the chip.

REFERENCES:
patent: 6303985 (2001-10-01), Larson et al.
patent: 6585905 (2003-07-01), Fan et al.
patent: 6661083 (2003-12-01), Lee et al.
patent: 6809408 (2004-10-01), Yu et al.
patent: 7145222 (2006-12-01), Gai
patent: 2004/0217450 (2004-11-01), Li et al.

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