Leadless semiconductor package

Details Leadless semiconductor package Leadless semiconductor package

2006-12-05

2006-12-05

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With dam or vent for encapsulant

C257S676000, C257SE23001

Reexamination Certificate

active

07145222

ABSTRACT:
A leadless semiconductor package mainly comprises a leadless lead-frame, a chip, a silver paste and a plurality of electrically conductive wires. The leadless lead-frame includes a chip paddle and a plurality of leads surrounding the chip paddle wherein the chip paddle has a cavity serving as a chip disposal area and a grounding area encompassing the cavity. The chip is disposed in the cavity so that the back surface of the chip faces the chip paddle and attached onto the chip paddle via the silver paste. Moreover, the chip is electrically connected to the leads. The grounding area is at the periphery of the chip paddle, and furthermore it is protruded from the chip disposal area so as to prevent the silver paste from overflowing on the grounding area. Thus, the electrically conductive wires will attach onto the grounding area well and enhance the electrical performance of the leadless semiconductor package.

REFERENCES:
patent: 6303985 (2001-10-01), Larson et al.
patent: 6585905 (2003-07-01), Fan et al.
patent: 6661083 (2003-12-01), Lee et al.
patent: 2004/0217450 (2004-11-01), Li et al.

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