Leadless semiconductor package

Details Leadless semiconductor package Leadless semiconductor package

2000-08-17

2002-06-04

Wille, Douglas (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

C257S690000, C257S670000, C257S692000, C438S123000

Reexamination Certificate

active

06400004

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to a lead frame package, and more specifically to a leadless semiconductor package.
2. Description of the Related Art
Lead frame packages has been used for a long period of time in the IC packaging history mainly because of its low manufacturing cost and high reliability. However, as integrated circuits products move its endless pace toward both faster and smaller in size, the traditional lead frame packages become gradually obsolete for some high performance-required packages. Thus BGA (Ball Grid Array packages) and CSP (Chip Scale Package) have emerged and become increasingly popular as a new packaging choice. The former was widely used in IC chips that have higher I/Os and need better electrical and thermal performance than the conventional packages, for examples, CPU and graphic chips. The latter has been widely used in mobile products of which the footprint, package profile, package weight are major concerns.
However, the lead frame package still remains its market share as a cost-effective solution for low I/O ICs. Traditional lead frame package has its limit of providing a chip scale and low profile solution due to the long inner leads and outer leads. Therefore, the semiconductor packaging industry develops a leadless package without outer leads such that both foot print and package profile can be greatly reduced.
FIG. 1
shows a bottom view of a leadless package
100
wherein the leads
110
a
are disposed at the bottom of the package as compared to the conventional gull-wing or J-leaded type package. The die pad
110
b
of the leadless package
100
is exposed from the bottom of the package thereby providing better power dissipation. Typically, there are four tie bars
110
c
connected to the die pad
110
b.
Due to elimination of the outer leads, leadless packages feature lower profile and light weight. Furthermore, due to the lead length reduction, the corresponding reduction in the resistance, conductance and capacitance make the leadless package
100
very suitable for RF (radio-frequency) product packages operating in several GHz to tens of GHz frequency range. It's also a cost-effective package due to its use of existing BOM (bill of materials). All the above-mentioned properties make the current leadless packages very suitable for telecommunication products such as cellular phones, portable products such as PDA (personal digital assistant), digital cameras, and IA (Information Appliance).
Conventional leadless packaging process comprises the following steps.
Firstly, a polyimide (PI) tape was attached to the bottom of a lead frame, this is to prevent the mold flash problem in the molding process. Typically, a lead frame (denoted as
105
in
FIG. 2
) for used in the MAP (mold array package) molding process comprises a plurality of units
110
each including a plurality of leads
110
a
arranged at the periphery of a die pad
110
b.
Each die pad
110
b
is connected to the lead frame
105
by four tie bars
110
c.
Then, referring to
FIG. 3
, IC chips
120
are attached to the die pads
110
b
using silver epoxy, and the epoxy is cured after die attach. After that, a regular wire-bonding process is used to make interconnections between the silicon chips
120
and the leads
110
a
of the lead frame
105
. After wire bonding, the lead frame
105
and the chips
120
attached thereon are encapsulated in a package body
130
. Typically, a MAP molding process was used to accomplish this encapsulation. The PI tape is then removed after the molding process. The molded product is then marked with either laser or traditional ink. Finally, post-mold curing and singulation steps were conducted to complete the packaging process. In the singulation process, a resin-bond saw blade is used to cut the molded product into separate units along predetermined dicing lines to obtain the finished leadless semiconductor packages. Typically, the leadless semiconductor package
100
is mounted onto a substrate, such as a printed circuit board (PC board), by using conventional surface mount technology (SMT).
One major problem during the manufacturing of the package occurred in the singulation process. Since the saw blade has to cut through two different materials, ie, the metal leadframe as well as the molding compound. This not only results in shorter blade life, but also creates lead quality problems such as metal burs created at the lead cutting ends
112
of the leads
110
a,
which will introduce unsatisfactory coplanarity of the finished packages thereby complicating and reducing the yield of the later SMT mounting process.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to overcome or at least reduce the problems and disadvantages associated with the above-described technique.
It is another object of the present invention to provide a leadless semiconductor package characterized in that the lower surface of each lead has an indentation formed corresponding to one of the bottom edges of the package and the indentation is embedded in the package body such that metal burs created at the lead cutting ends will not appear at the bottom of the package whereby the problems encountered in the surface mount process of the finished package can be avoided.
It is another object of the present invention to provide a lead frame for use in forming leadless semiconductor packages wherein the lead frame comprises a plurality of leads each having an indentation formed corresponding to a predetermined dicing line whereby the above-mentioned troubles during singulation can therefore be solved.
In accordance with the above listed and other objects we discloses a leadless semiconductor package mainly comprising a semiconductor chip disposed on a die pad and electrically connected to a plurality of leads arranged around the die pad. There are a plurality of tie bars connected to the die pad. The lower surface of each lead has an indentation formed corresponding to one of the bottom edges of the package. The semiconductor chip, the leads and the tie bars are encapsulated in a package body wherein the lower surface of each lead is exposed from the bottom surface of the package except the indentation thereof. During the encapsulating process, molding compound will flow into the indentation of each lead; hence, after curing, the indentation is embedded in the package body formed from the molding compound such that metal burs created at the lead cutting ends will not appear at the bottom of the package whereby the problems encountered in the surface mount process of the finished package can be avoided. In the leadless semiconductor package according to the present invention, the upper surface of each lead preferably has a cavity thereby enhancing the bonding between the leads and the package body.
The present invention further provides a lead frame for use in forming leadless semiconductor packages. The lead frame comprises a plurality of units each including a die pad and a plurality of leads arranged around the die pad. The die pad has an upper surface adapted for receiving a semiconductor chip. Each of the leads has opposing upper and lower surfaces wherein the upper surface thereof is coplanar with the upper surface of the die pad and the lower surface thereof has an indentation formed corresponding to a predetermined dicing line. Furthermore, in a preferred embodiment, each lead has a cavity defined in the upper surface thereof.


REFERENCES:
patent: 5894108 (1999-04-01), Mostafazadeh et al.
patent: 6166430 (2000-12-01), Yamaguchi
patent: 6208020 (2001-03-01), Minamio et al.

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