Leadless package

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices

Reexamination Certificate

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Details

C257S729000, C257S734000, C257S773000, C257S784000, C257SE23061, C257SE23141, C257SE23169, C228S180500

Reexamination Certificate

active

07808103

ABSTRACT:
Provided is a semiconductor package, and in particular a semiconductor package which is capable of electrically connecting to the outside without a lead. The leadless package includes a plurality of lower conducting layer patterns disposed separately from one another; an insulating layer pattern on the lower conducting layer patterns; a plurality of upper conducting layer patterns disposed separately from one another, on the insulating layer pattern; at least one semiconductor chip disposed on the upper conducting layer patterns; hole patterns formed through the upper conducting layer patterns and the insulating layer pattern, so that a part of the top surface of the lower conducting layer patterns are exposed; and electrical connectors electrically connecting: the at least one semiconductor chip and the upper conducting layer patterns; the upper conducting layer patterns and the lower conducting layer patterns exposed by the hole patterns; and the at least one semiconductor chip and the lower conducting layer patterns exposed by the hole patterns.

REFERENCES:
patent: 6806580 (2004-10-01), Joshi et al.
patent: 7061077 (2006-06-01), Joshi
patent: 7154186 (2006-12-01), Noquil et al.
patent: 7242076 (2007-07-01), Dolan
patent: 7268414 (2007-09-01), Choi et al.
patent: 7285849 (2007-10-01), Cruz et al.
patent: 7315077 (2008-01-01), Choi et al.
patent: 7335532 (2008-02-01), Noquil et al.
patent: 7371616 (2008-05-01), Jereza
patent: 7439613 (2008-10-01), Joshi et al.
patent: 7468548 (2008-12-01), Wu et al.
patent: 7504281 (2009-03-01), Joshi

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