Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material
Reexamination Certificate
2001-06-08
2003-08-26
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Insulating material
C257S707000, C257S779000, C257S778000, C257S782000, C257S777000, C257S737000, C257S738000
Reexamination Certificate
active
06611055
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally in the field of semiconductor chip packaging. More specifically, the present invention is in the field of leadless chip carrier design and structure.
2. Background Art
As microelectronic devices become more integrated with increased functionality and higher levels of performance, the complexity of the various packages, structures, or carriers that are used to house the semiconductor die itself grows proportionally. As a result of the increase in functionality and performance, among other things, the density of interconnects between semiconductor die and the structure or carrier that houses the die has correspondingly increased. Flip chip technology has emerged as one solution to the new challenges presented by the increase in density of interconnects between the semiconductor die and the structure that houses the die and which provides electrical connection to “off-chip” devices.
By way of background, flip chip technology is a surface mount technology wherein the semiconductor die is “flipped” over so that the active surface of the die faces the structure or carrier employed to house the die. In flip chip technology, the electrical contact between the die and the structure that houses the die is achieved through “solder bumps” that are placed on the active surface of the semiconductor die. In flip chip technology, “solder bumps” replace the conventional bonding wires used to provide electrical contact between the die and the structure that houses the die. Flip chip technology is often utilized in semiconductor devices running at high frequencies, such as RF (“Radio Frequency”) semiconductor devices. However, the use of flip chip technology in higher frequency devices, such as RF semiconductor devices, presents challenges in the manufacture of various packages, structures, or carriers that are used to house the “flip chip.”
Recently, “flip chips” have gained increased popularity over conventional dies using wire bond interconnects. A conventional die interconnects with a chip carrier through bond wires that connect the peripheral bond pads on the die to bond pads on the chip carrier. In contrast, a “flip chip” has an array of solder bumps on the active surface of the die that connect to pads on the “flip chip” carrier. Because a “flip chip” can connect to the “flip chip” carrier over the entire active surface of the die, the “flip chip” can support a larger number of interconnects than a die of similar size using wire bond interconnects.
There have been various attempts in the art to arrive at different chip carrier designs. Japanese Publication Number 10313071, published Nov. 24, 1998, titled “Electronic Part and Wiring Board Device,” on which Minami Masumi is named an inventor, discloses a structure to dissipate heat emitted by a semiconductor device. The structure provides metallic packed through-holes formed in a wiring board that transmit heat emitted from a bare chip through a heat dissipation pattern on the bottom of the wiring board, and then to a heat dissipation plate.
Japanese Publication Number 02058358, published Feb. 27, 1990, titled “Substrate for Mounting Electronic Component,” on which Fujikawa Osamu is named an inventor, discloses a substrate with a center area comprising eight thermally conductive resin-filled holes sandwiched between metal-plated top and bottom surfaces. An electronic component is then attached to the center area of the top metal-plated surface of the substrate with silver paste adhesive to improve heat dissipation and moisture resistance.
Japanese Publication Number 09153679, published Jun. 10, 1997, titled “Stacked Glass Ceramic Circuit Board,” on which Miyanishi Kenji is named an inventor, discloses a stacked glass ceramic circuit board comprising seven stacked glass ceramic layers. The multi-layer stacked glass ceramic circuit board further comprises a number of via holes comprising gold or copper with surface conductors on the top and bottom surfaces covering the via holes. The top conductor functions as a heat sink for an IC chip.
Japanese Publication Number 10335521, published Dec. 18, 1998, titled “Semiconductor Device,” on which Yoshida Kazuo is named an inventor, discloses a thermal via formed in a ceramic substrate, with a semiconductor chip mounted above the thermal via. The upper part of the hole of the thermal via is formed in a ceramic substrate in such a manner that it becomes shallower as it goes outward in a radial direction.
It is noted that an advantageous combination of the “flip chip” technology with conventional chip carrier structures has not been, hereinbefore, achieved. A conventional chip carrier structure for mounting a chip on a printed circuit board has a number of shortcomings. For example, conventional chip carriers still introduce too much parasitics and still do not provide a low inductance and resistance ground connection to the die. Conventional chip carriers also have a very limited heat dissipation capability and suffer from the concomitant reliability problems resulting from poor heat dissipation. As an example, in high frequency applications, such as in RF applications, several watts of power are generated by a single die. Since the semiconductor die and the chip carrier are made from different materials, each having a different coefficient of thermal expansion, they will react differently to the heat generated by the die. The resulting thermal stresses can cause cracking or a separation of the die from the chip carrier and, as such, can result in electrical and mechanical failures. Successful dissipation of heat is thus important and requires a novel structure and method.
Therefore, there exists a need for a novel and reliable structure and method to support, house, and electrically connect the “flip chip” to a printed circuit board while also overcoming the problems faced by conventional chip carriers. More specifically, there exists a need for a novel and reliable structure and method to support, house, and electrically connect the “flip chip” to a printed circuit board while providing low parasitics, efficient heat dissipation and a low inductance and resistance ground connection.
SUMMARY OF THE INVENTION
The present invention is directed to leadless flip chip carrier design and structure. The present invention discloses a flip chip structure and method for providing efficient dissipation of heat generated by the semiconductor die. The present invention further discloses a flip chip structure and method for providing low parasitics, and a low inductance and resistance ground connection.
In one embodiment, the present invention comprises a substrate having a top surface for receiving a semiconductor die with a number of solder bumps on its active surface. For example, the substrate can comprise organic material such as polytetrafluoroethylene material or an FR
4
based laminate material. By way of further example, the substrate can comprise a ceramic material. The present invention further comprises a printed circuit board attached to a bottom surface of the substrate.
In one embodiment, the invention comprises at least one via in the substrate. The invention's at least one via provides an electrical connection between a signal pad of the die and the printed circuit board. The at least one via can comprise an electrically and thermally conductive material such as copper. The at least one via provides an electrical connection between a substrate signal pad and the printed circuit board. The at least one via can abut or overlap the substrate signal pad. The substrate signal pad is connected to the signal pad of the die by a signal solder bump. The at least one via also provides an electrical connection between the signal pad of the die and a land that is electrically connected to the printed circuit board. Moreover, the at least one via can abut or overlap the land.
REFERENCES:
patent: 5309324 (1994-05-01), Herandez et al.
patent: 5506755 (1996-04-01), Miyagi et al.
patent: 5640048 (1997-06-01), Selna
pate
Farjami & Farjami LLP
Nguyen Joseph
Skyworks Solutions Inc.
Wilson Allan R.
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