Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2001-12-07
2004-09-07
Vigushin, John B. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S713000, C257S723000, C257S782000, C257S784000, C174S252000, C174S260000, C174S262000, C361S719000, C361S764000, C361S783000, C438S122000, C438S125000
Reexamination Certificate
active
06787895
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally in the field of semiconductor circuits. More specifically, the present invention is in the field of semiconductor die packaging.
2. Background Art
As businesses and individuals have become increasingly reliant on the information and communication provided via the Internet, the demand for greater bandwidth provided by high-speed broadband Internet services, such as DSL (“Digital Subscriber Line”) and cable modem services, has increased dramatically. In order to meet this demand and remain competitive, service providers of DSL services require DSL central site modems (“CSM”) with very high port density. Although high port density has been a market requirement for conventional digital CSMs for a number of years, the types of integrated circuits (“ICs”) used in DSL CSMs have presented a problem in increasing port density in those devices.
Is Conventional digital CSMs, such as digital V.90 CSMs, contain digital circuits that can be integrated to provide high port densities. DSL CSMs also include digital circuits that allow similar integration. However, in contrast to conventional digital CSMs, DSL CSMs also contain analog circuits, such as analog front ends (“AFE”) and line drivers, that do not allow the same type of integration as digital circuits. For example, the AFE and line driver ICs in DSL CSMs are required to dissipate heat generated from approximately one watt of power during operation. In order to dissipate the heat generated by the approximate one watt of power, the current approach is to provide special packaging for the DSL CSM die containing the line driver and AFE circuitry which does not lend itself to compact integration with high port densities.
For example, in order to dissipate the heat generated by the line driver and AFE circuitry of a DSL CSM, a single die containing the line driver and AFE circuitry is put into an Extended Thin Quad Flat Pack (“ETQFP”) package. The ETQFP package includes a metal slug with the die glued to the top surface of the metal slug using conductive thermal adhesive. The bottom surface of the metal slug is then soldered to a host printed circuit board (“PCB”) to allow, for example, a ground plane in the host PCB to distribute and dissipate the heat generated by the die throughout the host PCB. The metal slug in the ETQFP package and the ground plane in the host PCB are typically made of a good thermal conducting metal such as copper to facilitate the heat transfer from the die to the host PCB by reducing thermal resistance. Additionally, the host PCB can include vias located under the bottom surface of the metal slug in the ETQFP package to further facilitate the heat transfer from the die to the host PCB.
The ETQFP package approach discussed above is somewhat effective in dissipating heat generated by the line driver and AFE circuitry of a DSL CSM. However, the resulting ETQFP package is large in size and, further, does not allow for multiple dies to be placed in a single ETQFP package. Thus, because of the resulting large size of the ETQFP package, the ETQFP package approach currently used limits port density in a DSL CSM.
Therefore, there exists a need for a novel and reliable structure and method to support, house, and electrically connect multiple semiconductor dies to a PCB to overcome the problems faced by conventional semiconductor die packages. More specifically, there exists a need for a novel and reliable structure and method to support, house, and electrically connect multiple semiconductor dies to a PCB while providing sufficient heat dissipation and reduced thermal resistance to enable port density to be increased in a DSL CSM.
SUMMARY OF THE INVENTION
The present invention is directed to a leadless chip carrier for reduced thermal resistance. The invention discloses method and structure to support, house, and electrically connect one or more semiconductor dies to a printed circuit board while providing sufficient heat dissipation and reduced thermal resistance. According to one embodiment, a semiconductor die is situated in a cutout section of a substrate. The substrate can comprise, for example, a ceramic material or a fiber glass based laminate material, such as FR4. The semiconductor die can be attached to the substrate, for example, by epoxy. In one embodiment, the substrate is situated on a printed circuit board such that the semiconductor die situated in the cutout section of the substrate is situated on a support pad on the top surface of the printed circuit board. In one embodiment, a semiconductor die bond pad on the semiconductor die is connected to a substrate bond pad on the substrate. In one embodiment, an interconnect trace on the substrate is connected to an interconnect pad on the top surface of the printed circuit board.
Due to reduced thermal resistance between the semiconductor die and the support pad on the printed circuit board, the present invention provides a superior means for efficiently dissipating heat generated by the semiconductor die. Moreover, the present invention's efficient heat dissipation is further achieved in a multiple semiconductor die structure, wherein each semiconductor die is situated in a cutout section of the substrate over a respective support pad on the printed circuit board.
REFERENCES:
patent: 3777221 (1973-12-01), Tatusko et al.
patent: 5541450 (1996-07-01), Jones et al.
patent: 5543661 (1996-08-01), Sumida
patent: 5642261 (1997-06-01), Bond et al.
patent: 5663869 (1997-09-01), Vinciarelli et al.
patent: 5991156 (1999-11-01), Bond et al.
patent: 6133634 (2000-10-01), Joshi
patent: 6455926 (2002-09-01), Ho
Dadkhah Mahyar S.
Gizara Andrew R.
Hashemi Hassan S.
Jarcy Michael J.
McCarthy Evans S.
Farjami & Farjami LLP
Skyworks Solutions Inc.
Vigushin John B.
LandOfFree
Leadless chip carrier for reduced thermal resistance does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Leadless chip carrier for reduced thermal resistance, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Leadless chip carrier for reduced thermal resistance will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3187963