Patent
1983-07-22
1987-09-29
Sikes, William L.
357 80, H01L 2302
Patent
active
046972048
ABSTRACT:
A leadless chip carrier is constructed in such a manner that each of the electrode terminals is made to be recessed from the insulation layer of the bottom surface of the carrier so as to have a difference in level between the bottom surface and at least a part of the electrode terminal. Because of such construction, when the electrode terminals are bonded to the conductors of the printed circuit board in the reflowing method, molten solder is collected in the recessed portions of the electrode terminals besides each portion of the insulation layer positioned between the electrode terminals prevents flowing of the molten solder in the recessed portion, so that strength and reliability in the bonding are remarkably improved.
REFERENCES:
patent: 4288841 (1981-09-01), Gogal
patent: 4463217 (1984-07-01), Orcutt
patent: 4554575 (1985-11-01), Lucas
Arisawa Hiroshi
Katoh Ryoki
Mita Tsunemasa
Sekimoto Soichi
Shiratsuki Yoshiyuki
Fuji 'Xerox Co., Ltd.
Gonzalez Frank
Sikes William L.
LandOfFree
Leadless chip carrier and process for fabrication of same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Leadless chip carrier and process for fabrication of same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Leadless chip carrier and process for fabrication of same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1591829