Leading one/zero bit detector for floating point operation

Details Leading one/zero bit detector for floating point operation Leading one/zero bit detector for floating point operation

1993-02-10

1994-05-31

Mai, Tan V.

Boots, shoes, and leggings

364748, G06F 700, G06F 738

Patent

active

053175271

ABSTRACT:
A circuit is provided for using the input operands of a floating point addition or subtraction operation to detect the leading one or zero bit position in parallel with the arithmetic operation. This allows the alignment to be performed on the available result in the next cycle of the floating point operation and results in a significant performance advantage. The leading I/O detection is decoupled from the adder that is computing the result in parallel, eliminating the need for special circuitry to compute a carry-dependent adjustment signal. The single-bit fraction overflow that can result from leading I/O misprediction is corrected with existing circuitry during a later stage of computation.

REFERENCES:
patent: 4922446 (1990-05-01), Zurawski et al.
patent: 4926369 (1990-05-01), Hokenek et al.
patent: 5010508 (1991-04-01), Sit et al.
patent: 5075882 (1991-12-01), Sakai et al.
patent: 5204825 (1993-04-01), Ng

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