Leading edge blanking circuit

Details Leading edge blanking circuit Leading edge blanking circuit

1993-05-25

1995-05-23

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

327387, H03K 524

Patent

active

054184100

ABSTRACT:
A leading edge blanking circuit has been provided. The LEB circuit (20) includes a minimum number of components for monitoring a gate voltage of a transistor (28) and passing a current sense signal, which senses the current level through the transistor, to subsequent control circuitry (32) when the gate voltage exceeds a predetermined threshold (V.sub.LEBTH). Further, the predetermined threshold is chosen to be between the Miller plateau voltage of the transistor and the desired maximum gate voltage.

REFERENCES:
patent: 4914324 (1990-04-01), Goto
patent: 5027017 (1991-06-01), Fling
patent: 5162680 (1992-11-01), Norman et al.
patent: 5175451 (1992-12-01), Ihara
patent: 5206553 (1993-04-01), Imai et al.
International Application No. PCT/AU90/00208 having International filing date 21 May 1990, International Publication No. WO 90/14716, International Publication Date 29 Nov. 1990, and having Mark Raymond Kitson as the Inventor/Applicant.
UK Patent Document No. GB 2 257 855A having a Date of filing of 16 Jul. 1990, Application No. 9115658.8, and having Michael Lamoth as the inventor.

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